In a SPIE.TV interview, Joseph Sawicki, Vice-President and General Manager of the Design to Silicon division of Mentor Graphics, explains the challenges of moving from design abstraction to physical implementation to a successful yield.
“Design to silicon” is a complex process that continuously blends evolutionary trends, such as enhancements to 3D mask design and yield learning, with more revolutionary changes such as limiting the geometries and pattern options available to designers. How do we know what works? Design for test strategies insert circuitry into a design to enable us to determine if a device works properly after manufacturing. DFT helps fabless companies turn production designs into virtual test chips to help identify those “intersections” between the design and process that cause systematic issues. Armed with that knowledge, companies can then modify that issue out of the process and/or design flow.
Want to learn more about Mentor’s support for test and diagnosis? Click on the links below for more information…
- Getting a Clearer Picture (Semiconductor Engineering)
- Noise cancellation: The new failure and yield analysis superpower (Solid State Technology)
- A Goldmine of Tester Data (SemiWiki)
- A Flexible Test Strategy for 3D ICs (EE Journal)
- Improve test quality and reduce DFT costs (EDN)
- Testing Two Birds with One Stone (Evaluation Engineering)