With the move to small geometries, existing fault models such as stuck-at, transition, bridging, open, and small-delay are becoming less effective at ensuring desired quality levels. While these models only consider faults on cell inputs/outputs and interconnect lines between cells, more defects increasingly occur within the cell structures. A new cell-aware test that directly targets specific shorts, … Read More
Silicon Test and Yield Analysis Blog
Posts tagged with 'fault models'
16 Jan, 2014
- Friendly but Shy Bears, and other EOS/ESD Issues
- It's Electrifying!
- Manage Your Stress...Advice from the Experts
- Testing the Boundaries of Good Design
- Making the Impossible -- Dealing with Patterns Throughout the Design and Manufacturing Flow
- Failing to Succeed
- Global Warming
- Won't You Please, Please Help Me?
- 3D Yoga
- Little Orphan Annie
- September, 2014
- August, 2014
- July, 2014
- March, 2014
- February, 2014
- January, 2014
- October, 2013
- May, 2013