With the move to small geometries, existing fault models such as stuck-at, transition, bridging, open, and small-delay are becoming less effective at ensuring desired quality levels. While these models only consider faults on cell inputs/outputs and interconnect lines between cells, more defects increasingly occur within the cell structures. A new cell-aware test that directly targets specific shorts, … Read More
Silicon Test and Yield Analysis Blog
Posts tagged with 'Tessent'
16 Jan, 2014
- 3D Yoga
- Little Orphan Annie
- Esperanto for ICs
- Is your car safe to drive? Are you sure?
- Can You Benefit from Cell-Aware Test?
- Are you the 1%?
- Low Power, High Performance Design, Verification, and Test
- Apply Memory BIST to External DRAMs
- Automated Test Creation for Mixed Signal IP Using IJTAG
- Creating Plug-and-Play IP Networks in Large SoCs with IEEE P1687 (IJTAG)
- March, 2014
- February, 2014
- January, 2014
- October, 2013
- May, 2013