Optimizing yield and performance in a nanometer world
There are currently no dates scheduled for this event.
GLOBALFOUNDRIES / Mentor Graphics Seminar at DATE
Delivering a correct, high yielding product on time is the ultimate goal for a semiconductor development team. Reaching this goal becomes more and more difficult, as systematic defects to a larger degree are design specific. This event describes methodologies that drive yield of digital semiconductor devices through design and test data, augmenting traditional solutions. This flow can be implemented as a foundation of a collaborative process between fabless and foundry customers, benefiting both sides. It presents fast, high quality volume diagnosis and subsequent statistical analysis as two complementing technologies to carry out this methodology. The underlying technology key to the methodology is an extremely accurate and consequential single-die diagnosis of scan test failures. This gives failure analysis engineers or engineers involved in nondestructive testing and evaluation, a proven, very fast, and highly effective new way of defect localization and identification, complementing their traditional, hardware-based methods.
What You Will Learn
- Best practices for data collection and diagnosis of digital semiconductor devices in a fabless/foundry flow
- Techniques to pick the correct dies for an effective failure analysis
- Layout-aware diagnosis
- Diagnosis-driven yield analysis
- DFM-aware yield analysis
- Case studies based on 32nm and 28nm silicon data
Design, Automation & Test in Europe
International Congress Center
12 - 16 March, 2012 - Dresden, Germany
About the Presenters
Thomas Herrmann is MTS Product Engineer at GLOBALFOUNDRIES Yield Analysis Systems team focusing on Yield Learning through Scan Diagnosis. Previously, at AMD, Thomas was a member of the Dresden Design Center taking care of DFT, Test and Product Engineering as well as yield and defect analysis of a number of complex digital products. He earned his MS in computer science from the University at Jena, Germany.
Product Marketing Manager, Silicon Learning Products
Geir Eide is the Product Marketing Manager for the Silicon Learning Products in the Silicon Test Solutions Group at Mentor Graphics. Eide has been involved in semiconductor test and design-for-test for the last 15 years and has held positions as Development Engineering Manager and Technical Marketing Engineer at Mentor Graphics. Previously, Eide held an applications management position at Teseda Corporation. He earned BS and MS degrees in Electrical and Computer Engineering from the University of California at Santa Barbara.
Who Should Attend
- Engineers and managers responsible for physical design, test, quality, or yield of a product
- Engineers and managers responsible for product and technology bring-up
- Failure Analysis Lab Managers or Process Engineers
- Engineers involved in manufacturing production or process development
- Anyone involved with the financial impact of low yield or low product quality
- Better IP Test with IEEE P1687 and Tessent IJTAGhttp://www.mentor.com/products/silicon-yield/events/ip-test-with-tessent-ijtag Jun 5, 2013 : Austin, TX
- Mentor at SEMICON West 2013http://www.mentor.com/products/silicon-yield/events/semicon-west Jul 9, 2013 : San Francisco, CA (Moscone Center)