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Better IP Test with IEEE P1687 and Tessent IJTAG


This event will cover exciting developments related to the upcoming IEEE P1687 standard.

This new standard creates an environment for plug-and-play integration of embedded IP and a true IP pattern reuse methodology. The standard will play a critical role in helping design teams successfully integrate the growing amount of IP used in today’s complex designs. It will significantly simplify the design setup and test integration task at the die, stacked die, and system level, and provides access to embedded IP for the failure analyst. Tessent IJTAG, Mentor’s award winning new product, provides automation that goes far beyond just implementing P1687. Tessent IJTAG saves engineering time by automating design and test tasks, and significantly reduces the length of an aggregated test sequence for all the IP blocks in an SOC. This translates directly into faster production test readiness, reduced test time, and smaller tester memory requirements.

What You Will Learn

  • By the end of this event you will have a good understanding how P1687 can be of value for your IP-level pattern reuse and access needs. You will know key elements of P1687 and can appreciate the minimal design and methodology changes to your existing 1149.1-based approach when migrating to P1687. The examples shown in this event are derived from industrial use cases from early adopters of P1687.

About the Presenter

Presenter Image Martin Keim

Dr. Martin Keim joined the Silicon Test Solutions group of Mentor Graphics in 2001, where he is currently a senior technical marketing engineer and marketing lead for Mentor’s IJTAG products. Previously, he was a Test Engineer with Infineon Technologies in Munich, Germany. For several years, he has worked on the organizing committee of the International Symposium for Testing and Failure Analysis (ISTFA), and he is an active member of the IEEE P1687 working group. Dr. Keim was editor of the sixth edition of the Microelectronics Failure Analysis Desk Reference Manual and was responsible for the test and diagnosis chapters. He holds several national and international patents and is author of many technical publications. He received a doctorate in informatics from the Albert-Ludwigs University, Germany.

Who Should Attend

Seniors as well as novices from these areas: DFT managers, DFT engineers, DFT architects, DFT methodologist IP-, Chip-, System-Design managers and engineers IP-, Chip-, System-Test integrator Failure analysis managers and engineers System test managers, system test engineers

Products Covered

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