September 9-12, 2013
The cornerstone of test week
ITC is the world's premier conference dedicated to the electronic test of devices, boards and systems, covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement.
Mentor Graphics provides customers with the best-in-class technologies to address the test challenges of today’s most complex and advanced designs. Our comprehensive set of silicon test solutions include embedded memory test and repair, ATPG and test pattern compression, BIST for all portions of the design including high-speed Serdes I/O, and an extensive set of boundary scan capabilities. Our silicon learning solutions combine unique test bring-up, silicon characterization, diagnosis, and yield analysis capabilities that help users accelerate time to volume.
Conference Exhibit Hours
Free Exhibits Only - Registration All Days
|10:30 AM - 5:30 PM|
|9:30 AM - 4:30 PM|
|9:30 AM - 1:00 PM|
Register for ITC
Planning to go to ITC?
Join Mentor Graphics in Booth 211
Visit the Mentor Graphics booth #211 for informative presentations and product demos of the most comprehensive silicon test and yield analysis solutions for nanometer IC designs. Talk with our experts on the newest technology available.
Stop by for daily theater presentations on today’s hottest topics. The daily schedule will be posted outside the theater next to Mentor’s booth #211. These will be lively, interactive sessions presented by customers, industry leaders and hosted by Mentor Graphics. We will have a fantastic giveaway for everybody who attends a theater session!
Meet with Technology Experts
If you are interested in setting up a meeting with our technology experts, please make sure you contact us in advance. Send email to email@example.com
In our booth, learn about:
- Hybrid TK/LBIST which combines both compression and logic BIST solutions
- Cell-Aware test for automotive standards such as ISO 26262
- Unique test solutions for ARM processors and embedded memory IP
- 3D test for DRAM and logic
- Hierarchical solutions for large design efficiency and core plug-and-play reuse
- Automated IJTAG support for plug-and-play infrastructure and pattern generation
- Layout-aware diagnosis solutions for understanding and identifying yield loss from test data
Attend our Conference Sessions
Attend the technical papers Mentor Graphics and partners are presenting at ITC.
Sunday, September 8 | 8:30 – 12:00
Mixed-Signal DFT and BIST: Trends, Principles and Solutions
Presenter: S. Sunter
We start by briefly looking at trends in process, design, and analog/mixed-signal testing, then in more detail at trends in ad hoc design-for-test (DFT) and analog defect simulation. We then review standardized DFT suitable for mixed-signal circuits, including IEEE 1149.1, .4, .6, .8, and 1687. The trend analysis concludes with an analysis of BIST techniques, especially for ADC/DAC, but also for PLL, SerDes, DDR, and miscellaneous analogue. Next, seven essential principles of practical analog BIST are discussed, ranging from testing the BIST itself, and adding for precision, to subtracting for accuracy, and generating a digital result. Lastly, we discuss the most practical techniques to use in new DFT and BIST circuitry, ranging from the classic analog test bus, to mostly digital oversampling and undersampling circuits that improve measurement range, resolution, and reusability, to ultimately optimize quality and cost of test.
Tuesday, September 10 | 2:00 – 3:30
3.2 Fault Diagnosis of TSV-based - Interconnects in 3-D Stacked Designs
J. Tyszer, Poznan University of Technology; J. Rajski, Mentor Graphics
Tuesday, September 10 | 4:00 – 5:30
4.3 EDT Bandwidth Management, Practical Scenarios for Large SOC Designs
J. Tyszer, J. Janicki, Poznan University of Technology ; W-T. Cheng, Y. Huang, M. Kassab, N. Mukherjee, J. Rajski, Mentor Graphics; Y. Dong, G. Giles, Advanced Micro Devices
Tuesday, September 10 | 4:00 – 5:30
PANEL 2 Where Are the Waldos of DFT
J. Abraham University of Texas (Moderator) • R. Aitken, ARM (Organizer)
Whatever happened to the promised revolutions in DFT? Full-chip logic BIST, 1000X compression, defect-based testing, partial scan, and more. Our panel discusses why they are hard to find now and where they might be in the future.
Panelists. S. Davidson, Oracle, S. Ozev, Arizona State University, J. Rajski, Mentor Graphics, J. Rearick, AMD
Wednesday, September 11 | 8:30 – 10:00
7.2 Delay Testing and Characterization of Post-Bond Interposer Wires in 2.5-D ICs
S-Y. Huang, L-R. Huang, National Tsing Hua University, Taiwan; K-H. Tsai, W-T. Cheng, Mentor Graphics
Advanced Industrial Practices (AIP)
A 1.2 Is Silicon Another (the Last) Verification Engine?
S. Bailey, Mentor Graphics
Wednesday, September 11 | 12:00 – 2:00 - Poster Session
PO 31 Test Access Mechanism for TSV Characterization in 3D ICs
J.Ye, Y. Hu, X.Li, Institute of Computing Technology, CAS; R. Guo, R. Press, Y. Huang, L.Lai, W-T Cheng, Mentor Graphics; S-Y. Huang, National Tsing Hua University
Wednesday, September 11 | 2:00 – 4:00
10.2 On the Generation of Compact Test Sets
A. Kumar, C. Wang, S M. Reddy, University of Iowa; J. Rajski, Mentor Graphics
Thursday, September 12 | 1:00 – 2:20
15.1 Diagnosis and Layout-aware (DLA) Scan-Chain Stitching
J. Ye, UCAS; Y. Huang, W. Cheng, R. Guo, L. Lai, Mentor Graphics; Y. Hu, X. Li, ICT; W. Changchien, D. Lee, S. Eruvathi, K. Kumara, C. Liu, S. Pan, Taiwan Semiconductor Manufacturing Company
15.2 Design Rule Check on the Clock Gating Logic for Testability and Beyond
K-H. Tsai, S. Sheng, Mentor Graphics