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ITC 2014

October 21-23, 2014

ITC 2014

Join us at the International Test Conference 2014 at the Washington State Convention Center, Seattle, Washington in the beautiful Pacific Northwest. Mentor Graphics continues its support of ITC Test Week as a Platinum Supporter, Daily Passport Sponsor and a Sponsor of the 3D Test Workshop.

Planning to go to ITC? Register here


Washington State Convention Center

Seattle, WA

Register for Reception

Monday Evening Reception

Join us Monday, October 20, 2014 at 6:45 pm in the Convention Center in the North Galleria for a special technology reception. Our presenters, Janusz Rajski and Nilanjan Mukherjee, will talk about “The Next Big Thing in Test Compression. Registration will begin at 6:45 pm and our presentation will begin at 7:00 pm and follow with great food, beverages and music. Pre-registration is required.

The Next Big Thing in Test Compression!

Monday, October 20, from 6:45 pm – 9:00 pm, Washington State Convention Center, North Galleria

There will be a short presentation starting at 7:00 pm and will be followed for food, drink and music.

Register now

Join Mentor Graphics in Booth #304

Daily Prize Drawing

Daily Prize Drawing for each day 15 minutes before exhibits close! Must be present to win so bring a business card to enter (or we have some you can fill out).

Happy Hour

Join us for Happy Hour, Wednesday, from 3:30 PM to 5:00 PM.

Conference Exhibit Hours

October 21
10:30 AM - 5:30 PM
October 22
9:30 AM - 5:00 PM
October 23
9:30 AM - 1:00 PM

Conference Requires ITC registration

In Our Booth, Learn About:

The newest products and technology highlighting new features of the most comprehensive silicon test and yield analysis solutions for nanometer IC designs

  • Hierarchical solutions for large design efficiency and core plug-and-play reuse (industry success)
  • Hybrid TK/LBIST which combines both compression and logic BIST solutions
  • Cell-Aware test for automotive standards such as ISO 26262
  • Unique test solutions for ARM processors and embedded memory IP
  • 3D test for DRAM and logic
  • Automated IJTAG support for plug-and-play infrastructure and pattern generation
  • RCD solutions for understanding and identifying yield loss from test data

Theater Schedule

Location: Mentor Theater in Booth 304

Tuesday, 10:40 am Tessent Embedded Compression - the next big thing!
Tuesday, 11:00 am Cell-aware experiences in a high-quality automotive test suite
Tuesday, 11:20 am The next big thing - product results!
Tuesday, 11:40 am The ARM MBIST Information File: Electronic Documentation of the ARM MBIST Interface
Tuesday, 3:35 pm Using DFT Techniques for ATPG
Wednesday, 10:05 am Resolving yield excusions with scan diagnosis analysis
Wednesday, 1:30 pm Cell-aware diagnosis results and experiences
Thursday, 10:35 am Hierarchical DFT industry usage

Attend our Conference Sessions

Attend the Technical Sessions presented by Mentor Graphics and its Customers and Partners


Sunday, October 19 | AM only

Tutorial: Mixed-Signal DFT and BIST: Trends, Principles and Solutions

Presenter: Steve Sunter

We analyze recent trends in IC processes and design, and implications for test, then look at trends in testing. Next, we discuss trends in ad hoc DFT and fault simulation, then IEEE DFT standards 1149.1, .4, .6, .7, .8, P1149.10, and P1687. The trend analysis concludes with a review of BIST techniques. Addressed circuits include PLL/DLL, ADC/DAC, SerDes/DDR, general I/Os, random analog, and (briefly) RF. Next, seven essential principles of practical analog BIST are presented. Lastly, we discuss practical DFT techniques, ranging from analog defect simulation and classic analog bus, to oversampling and undersampling methods that greatly improve range, resolution, and reusability.

Monday, October 20 | 1:00 – 4:30

Tutorial: Hierarchical Scan Compression

Presenter: Yu Huang, Brion Keller, Cadence, Adam Cron, Synopsys

This tutorial covers fundamental concepts, recent developments and industry practices on scan compression in SoC hierarchical test flow. The tutorial starts with a discussion on compression technologies for a single design, followed by hierarchical DFT methodologies and techniques such as TAM/ wrapper/test scheduling, diagnosis, etc., IEEE test standards such as 1149.1, 1500 and P1687 will be introduced. Finally, it demonstrates the latest hierarchical compression technologies, flows and solutions from three leading EDA companies. Each company introduces its own complete DFT and ATPG flow to integrate the state-of-art compression technologies into the hierarchical core-based SoC designs.


Monday, October 20 | 4:30 – 6:00

Panel 1: Analog Design-for-Test: What's the Real Story?

Robert Aitken, ARM (Moderator); Mani Soma, University of Washington (Organizer)

Analog design-for-test (DFT) and mixed-signal DFT have made rapid progress in the last 10 years, with many new ideas presented at worldwide conferences and published in journals. Yet an examination of recent advances in design shows a rather surprising missing link: analog designers rarely, if at all, use any of the published DFT methods in their designs; they choose their own methods instead, and incorporate them during design time. Recent hot topics, e.g., design-for-self-healing, design-for-calibration, adaptive designs, etc., make this missing link even more puzzling. The question remains why analog designers are not utilizing the methods published by analog DFT researchers, and why analog DFT researchers have not re-used or enhanced methods already demonstrated by analog designers.

Panelists: Terri Fiez (Oregon State University), Sandeep Kumar (Silicon Labs), Jeyanandh Paramesh (Carnegie Mellon University), Stephen Sunter (Mentor Graphics)

Tuesday, October 21 | 4:00 – 5:30

Panel 2: Open Problems in Design, Verification, and Test: Why Is It (Not) Business as Usual?

Tim Cheng, UC Santa Barbara, (Moderator); Rubin Parekhji, Texas Instruments (Organizer)

Panelists with wide-ranging technical and business expertise will discuss open problems in design, verification and test. Solutions to these open problems are critical for future electronic systems that will incorporate massive integration of diverse functionality with unprecedented constraints on cost, power/performance, reliability and time-to-market. The panelists will also debate whether existing design-EDA partnerships are adequate or a new ecosystem is required to meet future application needs.

Panelists: Sanjive Agarwala (Texas Instruments), Paul Cunningham (Cadence Design Systems), Stephen Pateras (Mentor Graphics), Ruchir Puri (IBM), Ramesh Senthinathan (Broadcom), Srikanth Venkataraman (Intel)

Technical Papers

Session 2.3 Practical random sampling of potential defects for analog fault simulation

Presenters: Stephen Sunter, Krzysztof Jurga (Mentor), Peter Dingenen, Ronny Vanhooren (ON Semiconductor)

Session 6.2 Isometric Test Compression with Low Toggling Activity

Presenters: J. Tyszer (Poznan U T), Mark Kassab, Amit Kumar, Elham Moghaddam, Nilanjan Mukherjee, Janusz Rajski (Mentor Graphics), S.M. Reddy (Univ of Iowa) C Wang, Mentor Graphics

Session 7.3 Fast BIST of I/O Pin AC Specifications and Inter-Chip Delays

Presenters: Stephen Sunter (Mentor Graphics), Saghir Shaikh (Broadcom), Qing Lin (Broadcom)

Session 22.2 Invited Speaker, Emulation and its Connection to Test

Presenters: Kenneth Larsen, Mentor Graphics

As electronic chip designs are predominately System-On-Chip (SoC), hardware emulation has become a crucial tool for pre-silicon hardware and software validation. Pre-silicon emulation models are often available many quarters before tapeout and are used in many areas such as OS boot, software driver development, and system stress and performance testing. Increasingly hardware emulation is used in the development of test contents and to verify the quality of tools and processes used in post-silicon testing. This presentation will cover how hardware emulation aids pre- and post-silicon testing and debugging of SoC infrastructure functions for testability, reliability, and repairability.


Wednesday, October 22 | 12:00 - 2:00

Rapidly Sourcing Yield Excursions with Scan Analysis

Presenter: Earl McArthur, Cypress Semiconductor, Bill Keller, Mentor Graphics

This poster demonstrates how noise-reducing statistical enhancement of layout aware scan diagnosis results provided process layer identification and FA direction for solving a large yield problem in manufacturing.


Thursday and Friday, October 23 - 24

3d Test Workshop

Online Chat