ITC 2011
The cornerstone of test week
ITC is the world's premier conference dedicated to the electronic test of devices, boards and systems, covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement.
Mentor Graphics provides customers with the best-in-class technologies to address the test challenges of today’s most complex and advanced designs. Our comprehensive set of silicon test solutions include embedded memory test and repair, ATPG and test pattern compression, BIST for all portions of the design including high-speed Serdes I/O, and an extensive set of boundary scan capabilities. Our silicon learning solutions combine unique test bring-up, silicon characterization, diagnosis, and yield analysis capabilities that help users accelerate time to volume.
Conference Exhibit Hours
Free Exhibits Only
Registration All Days
| Tuesday, September 20 | 10:30 AM - 5:30 PM |
| Wednesday, September 21 | 9:30 AM - 4:30 PM |
| Thursday, September 22 | 9:30 AM - 1:00 PM |
Visit Our Booth
Visit the Mentor Graphics booth #217 for informative presentations and product demos of the most comprehensive silicon test and yield analysis solutions for nanometer IC designs. Stop by for daily theater presentations on today’s hottest topics. The daily schedule will be posted outside the theater next to Mentor’s booth #217. These will be lively, interactive sessions presented by industry leaders and hosted by Mentor Graphics.
See what the celebration is all about in the Mentor booth. Talk with any of our Mentor representatives throughout the conference and get your Disney® Dollar certificate redeemable at Trader Sam’s Enchanted Tiki Bar in the Disneyland Hotel.
Demos and presentations of the latest products highlighting new features will be available on demand from our technical experts during the conference.
In our booth, learn about:
- New approaches being used to improve test quality
- Mentor’s unique solution for accurate volume diagnosis of production test failures
- Mentor’s complete solution for testing embedded memory in SOC designs
- The industry’s leading ATPG and compression solutions
- Visit Mentor Graphics and find out how to win an Apple® iPad® 2 during the conference and exhibits
Technical Presence
Attend the technical papers Mentor Graphics and partners are presenting at ITC. Topics include: Low Power Compression, Cell-aware Analysis, DFT and Test Flows for Stacked Die, Deterministic IDDQ, Mixed-Signal DFT and BIST, Challenges and Best Practices in Advanced Silicon Debut presented at technical sessions, panels, tutorials and workshops.
Sunday 8:30 – 4:30
Tutorial: Mixed-Signal DFT and BIST: Trends, Principles & Solutions
Presenter: S. Sunter
Attendees will gain a clear understanding of trends in IC processes and design, in testing, and in standardized DFT, learn seven essential principles of practical analog BIST, and review the most-practical DFT and BIST techniques. Learn why analog BIST always seems to be a future solution, and how to make parametric DFT, diagnosis and testing systematic. Examples and case studies are included.
Monday 4:30 – 6:00
Panel: Industry Leaders Panel--How Will Testing Change in the Next 10 Years?
P. Nigh, IBM (Moderator/Organizer)
Panelists:B. Cory, NVIDIA * W. Eklow, Cisco Systems * D. Josephson, Intel * R. Madge, GLOBALFOUNDRIES, J. Rajski, Mentor Graphics * E. Volkerink, Advantest Verigy Group
Industry test experts talk about how the testing industry will change in the next 10 years. How will test equipment, design-for-test, EDA software, test steps/processes--and the companies that support these--be changing.
Tuesday 2:00 – 3:30
Lecture: Partner Conference Showcase
ISTFA: When Test Meets FA...
M. Keim, Mentor Graphics
Tuesday 4:00 – 5:30
Panel: Challenges and Best Practices in Advanced Silicon Debug
J. Rearick, AMD (Moderator) • J. Zeng, AMD (Organizer)
Panelists: H. Chen, MediaTek Wirelewss; W.Cheng, Mentor Graphics, M. Kamm, Cisco Syhsstems, P. Pant, Intel, E. Rentschler, AMD
This panel will discuss whether structural-based tests, including at-speed scan tests, test-structure-based parametric tests etc., can have a greater role to play in debugging performance and power related issues. The advantages and disadvantages of system test versus structural test for validation will also be explored.
Wednesday 8:30 – 10:00
Paper: Low-Power Compression Utilizing Clock Gating
E.K. Moghaddam, S.M. Reddy, University of Iowa • J. Rajski, Mentor Graphics
This paper presents a new low-power compression scheme to simultaneously reduce test data volume and test power. The result is acceleration of the test application time and an increase in the number of cores that can be tested in parallel.
Wednesday 10:30 – 12:00
Paper: Cell-aware Analysis for Small-Delay Effects and Production Test Results from Different Fault Models
F. Hapke, J. Schloeffel, W. Redemund, A. Glowatz, J. Rajski, Mentor Graphics • M. Reese, J. Rearick, J. Rivers, AMD
This paper presents a new approach to significantly improve the overall defect coverage for CMOS-based designs with the final goal to eliminate any system-level test . It describes the pattern generation flow for detecting cell-internal small-delay defects.
Wednesday 12:00 – 2:00
Poster: Using Scan Diagnosis Analysis to Improve Fab Process Debug
S. Palosh, Freescale Semiconductor, G. Eide, Mentor Graphics
Wednesday 2:00 – 4:00
Paper: Adaptive Parametric BIST of HighSpeed Parallel I/Os via Standard Boundary Scan
S. Sunter, A. Roy, Mentor Graphics
Improvements are shown for an I/O BIST first published at ITC10. Silicon results show 5-ps resolution for any range, for crosstalk, duty cycle, and skew, at DDR speeds. It can test each versus the average value measured for any group of pins.
Thursday 8:30 – 10:00
Paper: EDT Channel Bandwidth Management in SOC Designs with Pattern-independent Test Access Mechanism
J. Tyszer, J. Janicki, Poznan University of Technology; A. Dutta, M. Kassab, G. Mrugalski, N. Mukherjee, J. Rajski, Mentor Graphics
The paper presents a new channel allocation method for higher EDT compression in SOC designs comprising isolated cores. It combines a test data reduction technique with power-aware test scheduling and pattern-independent test access mechanisms.
Thursday 8:30 – 10:00
Paper: A Novel Test Access Mechanism for Failure Diagnosis of Multiple Isolated Identical Cores
M. Sharma, A. Dutta, W-T. Cheng, B. Benware, M. Kassab, Mentor Graphics
We present a novel TAM for chips with multiple isolated identical cores through which all the cores can be tested in parallel and at the same time accurate failure diagnosis can be achieved while using similar test resources as a single core.
Thursday 8:30 – 10:00
Paper: Deterministic IDDQ Diagnosis Using a Net-Activation-based Model
A. Kun, R. Arnold, P. Heinrich, G. Maugard, Infineon Technologies; H. Tang, W. Cheng, Mentor Graphics
In this paper, a fast simulation-based method is presented to diagnose single- or multiple IDDQ failures in digital logic. The results are verified on real silicon.
Thursday and Friday
Workshop: 2nd IEEE International Workshop on Testing Three-Dimensional Stacked ICs
DFT and Test Flows for Stacked Die
David Buck and Stephen Pateras