ITC 2009
ITC is the world's premier conference dedicated to the electronic test of devices, boards and systems, covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement.
Visit Our Booth
Visit the Mentor Graphics booth #217 for informative presentations and demonstrations of the most comprehensive silicon test and yield analysis solutions for nanometer IC designs.
Hours
- Tuesday, November 3rd:
10:30 AM – 5:30 PM - Wednesday, November 4th:
9:30 AM – 5:30 PM Free Exhibits after 1:00 - Thursday, November 5th:
9:30 AM – 2:00 PM Free Exhibits all day
In our booth, learn about:
- Why today’s nanometer IC designs require higher test pattern compression for improving test quality while controlling test costs
- Mentor’s unique solution for accurate volume diagnosis of production test failures
- Mentor’s complete solution for testing embedded memory in SOC designs
- The industry’s leading ATPG and compression solutions
Mentor Graphics and LogicVision
The combined silicon test solutions from Mentor Graphics and LogicVision provide customers with the best-in-class technologies to address the test challenges of the digital logic and memory portions of their designs, as well as the increasingly common high-speed SerDes analog and DDR-based interfaces. LogicVision’s unique test bring-up and silicon characterization tools — combined with Mentor’s leading failure diagnosis capabilities — help users accelerate yield ramp, reducing time-to-volume.
Mentor Graphics meets the needs facing the industry with the most comprehensive set of silicon test solutions for thorough testing and yield learning for design logic and embedded memory arrays, including ATPG, test pattern compression, BIST, boundary scan, and failure diagnosis.
Evening Reception
Join us on Tuesday, November 3, 2009, from 7-9 pm at the Hilton Hotel, Salon J, 6th Floor, directly across from the Austin Convention Center.
This will be your opportunity to hear from Mentor Graphics on the future of silicon test and how the recent acquisition of LogicVision will enhance Mentor’s roadmap.
Enjoy mingling, food and beverage. And, of course, no evening would be complete without some of the finest entertainment Austin offers. Be ready to learn about test!
Doors open at 7 pm immediately following the ITC Poster Session at the Convention Center. Don’t be late. You won’t want to miss any part of this event!
Technical Presence
Attend our Mentor Graphics Design-for-Test technical sessions which include topics such as: Increasing defect coverage of test patterns, BIST based fault diagnosis for embedded memories, How to reach compression ratios approaching 1000x, and Panel sessions.
Tuesday 1:30 PM – 3:30 PM
1.2 Defect-Oriented Cell-Aware ATPG and Fault Simulation for Industrial Cell Libraries and Designs
F. Hapke, R. Krenz-Baath, A. Glowatz, J. Schloeffel, Mentor Graphics; H. Hashempour, S. Eichenberger, C. Hora, D. Adolfson, NXP Semiconductor
A new cell-aware methodology is proposed to significantly increase the defect coverage of test patterns generated by ATPG. The used fault model is directly targeting layout-based intra-cell faults. CA-ATPG has been evaluated on 90-nm/65-nm technologies and reduces the escape rate by 8.4 ppm/mm2.
Tuesday 1:30 PM – 3:30 PM
2.1 Testing Bridges to Nowhere—Combining Boundary Scan and Capacitive Sensing
S. Sunter, Mentor Graphics; K. Parker, Agilent Technologies
Learn how ICs with the proposed IEEE 1149.8.1 standard can detect opens and shorts in signal wires (including differential) connected to empty sockets, passives, or nonscannable ICs
Tuesday 4:00 PM – 5:00 PM
Panel 2 Can EDA Help Solve Analog Test and DFT Challenges?
C. Moore, Maxim Integrated Products (Moderator) • R. Datta, Texas Instruments and S. Sunter, Mentor Graphics (Organizers)
This panel will explore whether and where the EDA industry could improve DFT and testing of analog functions.
Panelists: K. Arabi, Broadcom • C. Force Texas Instruments • S. Sunter, Mentor Graphics • N.Nandra, Synopsys • S.Taneja, Cadence Design Systems
Wednesday 8:30 AM – 10:00 AM
7.1 Fault Diagnosis for Embedded Read-only Memories
J. Tyszer, Poznan University of Technology; N. Mukherjee, A. Pogiel, J. Rajski, Mentor Graphics
A BIST-based fault diagnosis is presented for embedded read-only memories. Test logic highly reduces data that needs to be preserved to identify failing bit-maps and minimizes the download time. The approach allows collection and processing of fail logs while BIST is running at system speed.
Wednesday 10:30 AM – 12:00 PM
9.2 Compression Based on Deterministic Vector Clustering of Incompatible Test Cubes
J. Tyszer, D. Czysz, Poznan University of Technology; G. Mrugalski, N. Mukherjee, J. Rajski, Mentor Graphics
The presented solution is the third-generation compression scheme that uses deterministic clustering of incompatible test cubes and encompasses three data reduction features in one on-chip decoding system. It offers compression ratios of order 1000X with encoding efficiency much higher than 100%.
Thursday 2:00 PM – 3:30 PM
17.3 Test Point Insertion Using Functional Flip-Flops to Drive Control Points
J. Yang, N. Touba, The University of Texas at Austin; B. Nadeau-Dostie, Mentor Graphics
A novel methodology to reduce the area overhead for test point insertion is presented in which functional flip-flops are used to drive control test points instead of using test-dedicated flip-flops.