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Mentor Forum - Hierarchical DFT for large SOC designs

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Overview

The growing complexity of SOC designs year on year is causing large runtimes during pattern generation with increasing memory requirements. Historically, this was seen on network, telecommunications and multimedia chips. Nowadays, some consumer and automotive chips are in the same situation as more and more IP blocks are incorporated. Additionally, when testing these large chips, power under test is becoming an issue as chips can overheat due to the high level of switching or fail due to abnormal current consumption causing a voltage drop on the power rails.

Dr. Janusz Rajski director of engineering for Mentor's DFT and IEEE fellow states "Hierarchical DFT dramatically reduces run times, memory requirements and pattern counts. It is an essential enabler of high productivity in the design of large SOCs.“

The EDA industry has attempted to address these technical problems by improving DFT tool performance but there is always a limit. DFT engineers have tried creative methods to schedule the production patterns but again hit various limitations. Some DFT engineers have realised a more robust and reliable solution lies in developing a hierarchical DFT architectural methodology. This seminar will discuss and present the technical challenges and the hierarchical DFT solution that many companies are starting to adopt as a standard DFT methodology.

What You Will Learn

  • DFT Technical challenges on large SOC designs and the motivation for Hierarchical DFT
  • DFT Architecture discussion
  • Benefits and Value of an Hierarchical DFT methodology
  • Overview of Mentor Graphics Hierarchical DFT solution

About the Presenter

Presenter Image Rick Fisette

Rick is a 25 year veteran of the Design-For-Test industry working at the system, board and ASIC levels. Prior to joining Mentor Graphics’ Silicon Test Solutions group as a technical marketing engineer, Rick worked in the ASIC industry providing DFT consulting services for a variety of customers and design types. His specialty has been ATPG and BIST solutions with a particular focus on DFT methodologies and architectures. He works with customers to teach them hierarchical DFT techniques and feed their requirements back into product development.

Publications include: - Boost DFT Efficiency for Large SoCs | Rick Fisette | EDN, April 23, 2013 - What’s the Difference Between Scan ATPG and IJTAG Pattern Retargeting | M Keim, M Kassab, R Fisette | Electronic Design, Jan 22, 2013

Who Should Attend

  • Engineering managers responsible for manufacturing test costs and outgoing product quality levels
  • DFT and Test Engineers responsible for the generation and/or application of manufacturing test patterns

Products Covered

 
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