Power-Aware Silicon Test: Understanding Testing and Power-Sensitive Designs Webinar
There are currently no dates scheduled for this event. However a recording of a previous session is available as an on-demand web seminar.
View This On-Demand Web Seminar NowOverview
Over the last few years, managing power during test has become more important, and more challenging. Designers tend to focus on 2 areas when it comes to silicon test and power; low-power ATPG and power-aware test.
During silicon test, test-vector volume and execution time are tracked to minimize the cost of test. As a result, the goal for automatic test pattern generation (ATPG) is to achieve the maximum coverage with the minimum number of test patterns. This produces a conflict with the goal of managing power and testing power domains, because, to get the highest quality test results, the IC under test can be operated beyond its normal functional modes. This can result in false failures and in some cases will affect product reliability or cause permanent damage to the IC. Controlling the switching level during automatic test program generation (ATPG) to stay within the power budget is important for low-power ATPG.
Devices that are designed for use in low-power applications include many structures to manage power. In addition to functional logic to control power, these designs also use retention cells, to remember the last-state of the logic prior to power-down, isolation cells, and level shifters. Power-aware silicon test solutions must identify, manage and accurately test these features in order to guarantee high-quality devices.
This talk will discuss the trends, drivers and solutions for power-aware test that have emerged. We will discuss the technologies where power-aware test required, and, how designers are looking to address these issues. We will also discuss the impact power-aware test has on test planning and on test generation.
What You Will Learn
- Designs approaches which are in the forefront of low power test
- Compelling reasons for addressing low power test issues
- The test solutions available for low power test
About the Presenter
Kan Thapar
Kan Thapar is the European Product Specialist for the Mentor Graphics Test tools. He works with leading global electronic companies in Europe and India at the technical management level on addressing their crucial test needs for high volume products. This involves high level management meetings on understanding their needs and promoting Mentor Graphics test tools. He is participating in various collaborative initiatives to introduce advanced test methodologies to these Mentor customers. He has organised technology seminars on Test for the European customers, as well as, expert panels for the DATE conferences. He has been co-author on papers in technical test journals. He has been with Mentor Graphics for 14 years and has previously supported the Design Entry, Simulation, Emulation, Formal Verification, ASIC Synthesis and Test products in a technical sales capacity.
Before joining Mentor Graphics, he was at GEC Hirst Research Centre where he managed a project team to design ASICs for Telecommunications products. He has extensive and in-depth experience as a VLSI and ASIC designer for multi-media, DSP and military products from conception to tapeout. He published papers internally and for EU electronic collaborative projects such as ESPRIT and the UK Alvey projects.
He holds a B.Sc. in Mathematics and a M.Sc. in Digital Systems. He has completed an Open University course on Effective Management.
Who Should Attend
- DFT Engineers & Managers
- Design engineers who deal with designs below 90 nm, multi-million gate and functional clocks > 150MHZ
- Engineers working on consumer designs such as multimedia and mobile phones and low power designs
Products Covered
Technical Requirements
What do I need to watch and hear this web seminar?
Mentor Graphics’ web seminars are delivered using Adobe Connect. To watch the seminar all you need to have installed is the Adobe Flash Player, version 8 or later on Windows, Macintosh, Linux, and Solaris. The Flash Player is already installed on over 98% of internet connected computers worldwide so you will not have to install any software prior to attending the meeting. You will be able to login to the seminar room 15 minutes prior to the start time on the day of the presentation. You can hear the audio using your computer’s speakers via VoIP (Voice over IP) and background music will play prior to the beginning of the presentation.
Detailed system requirements
Microsoft® Windows Vista® Home Basic, Home Premium, Ultimate, Business, or Enterprise (32-bit edition)
- Microsoft Internet Explorer 7 or later
- Mozilla Firefox 2
- Adobe Flash® Player 8 or later
Microsoft Windows® XP Professional or Home Edition with Service Pack 2
- Microsoft Internet Explorer 6, 7
- Mozilla Firefox 1.x, 2.x
- Mozilla 1.x or later
- Netscape 7.x
- Adobe Flash Player 8 or later
Microsoft Windows 2000 with Service Pack 4
- Microsoft Internet Explorer 5.x
- Mozilla Firefox 1.x, 2.x
- Mozilla 1.x
- Netscape 8
- Adobe Flash Player 8 or later
Windows hardware requirements
- Intel® Pentium® II 450MHz or faster processor or equivalent (1GHz recommended when screen sharing)
- 128MB of RAM
Mac OS X v10.4, 10.5 (Intel)
- Firefox 1.5.0.3, 2.x
- Safari 2.x
- Adobe Flash Player 8 or later
Mac OS X v10.4 (PowerPC®)
- Safari 1.x, 2.x
- Firefox 1.x
- Mozilla 1.x
- Netscape 7.x or later
- Adobe Flash Player 8 or later
Mac OS hardware requirements
- PowerPC G3 500MHz or faster or Intel Core™ Duo 1.83GHz or faster processor
- 128MB of RAM
Linux:
- Red Hat® Enterprise Linux® (REHL) 3 update 8; RHEL 4 update 4 (AS/ES/WS); Novell SUSE® 9.x or 10.1
- Mozilla Firefox 1.5.0.7, 2.x
- Mozilla 1.7.x
- SeaMonkey 1.0.5
- Processor: Modern processor 800MHz or faster (1GHz recommended)
- Memory: 512MB of RAM; 128MB of graphics memory
- Adobe Flash Player 9 or later
Solaris™
- Mozilla 1.7
- Adobe Flash Player 9 or later
Additional requirements
- Minimum bandwidth 56Kbps