Achieving Significant Quality Improvements with the Cell-Aware Test Methodology
Traditional fault models and associated test patterns are becoming increasingly less effective at achieving desired silicon quality levels. The new Cell-Aware test methodology which models and targets defects within each cell addresses inherent limitations of traditional testing to achieve significant reductions in defective part (DPM) levels.
This seminar will cover all aspects of this exciting new test methodology. Details of the underlying technology will be reviewed as well as a description of the cell library characterization flow necessary for creating new Cell-Aware fault models. Pattern and coverage results for several industrial designs will be presented as well as silicon test results gathered over several million parts. Cell-internal diagnosis and physical failure analysis results will be presented confirming that Cell-Aware tests detect real physical defects. The ability of the Cell-Aware methodology to effectively address FinFET related defect types will also be covered.
What You Will Learn
You will gain an understanding of the theory behind the Cell-Aware test methodology and the flows necessary to create Cell-Aware fault models. More importantly you will learn how this new methodology can significantly improve the quality of your parts and ultimately help improve yield as your organization moves to new technology nodes.
About the Presenter
Dr. Martin Keim joined the Silicon Test Solutions group of Mentor Graphics in 2001, where he is currently a senior technical marketing engineer and marketing lead for Mentor’s IJTAG products. Previously, he was a Test Engineer with Infineon Technologies in Munich, Germany. For several years, he has worked on the organizing committee of the International Symposium for Testing and Failure Analysis (ISTFA), and he is an active member of the IEEE P1687 working group. Dr. Keim was editor of the sixth edition of the Microelectronics Failure Analysis Desk Reference Manual and was responsible for the test and diagnosis chapters. He holds several national and international patents and is author of many technical publications. He received a doctorate in informatics from the Albert-Ludwigs University, Germany.
Who Should Attend
- Engineering managers responsible for manufacturing test costs and outgoing product quality levels.
- DFT and test engineers responsible for the generation and/or application of manufacturing test patterns.
- Product and test engineers responsible for the diagnosis of semiconductor failures.
- Engineers responsible for the generation and maintenance of cell libraries
Improve Logic Test with a Hybrid ATPG/BIST Solution
Two test strategies are used to test virtually all IC logic—automatic test pattern generation (ATPG) with test pattern compression, and logic built-in self-test (BIST). For many years, there was a...
Tessent Product Suite Overview
Built on the foundation of the best-in-class test tools for each test discipline, Tessent® brings these solutions together in a powerful test platform that ensures total chip coverage.
The Defect-Free & High Yield DFT Solution for ARM IP
ARM and Mentor Graphics have teamed up to provide their partners with DFT flows to deliver ARM-based products to the market in a timely manner, free from manufacturing defects and together with a high yield.