Tessent MemoryBIST - How to get the most from your tool
The move to 65nm and below is creating significant challenges to product quality and cost. With the move to these smaller geometries new types of defect mechanisms emerge due to unexpected interactions between the physical design and the variability in the manufacturing process. Without an effective silicon test strategy attempting to maintain high quality can cause testing costs to skyrocket. Amplifying these silicon test challenges is the growing complexity of SoCs where block-based design methods mean that a wide variety of functions, coming from different design teams or IP providers, turn full-chip testing into a significant endeavor. Further, packaging has not enabled test I/O to scale with circuit size, thus limiting test access. Insufficient test strategies utilizing various point tools can result in gaps in test coverage, thereby incurring significant risk to the device shipped and the systems in which it is a part. Time-to-market is also a concern for those companies embarking on bringing to market products based upon advanced IC technologies. Tasks such as test bring-up and first silicon debug must be done quickly.
This workshop will introduce Mentor’s new Tessent product platform which provides a holistic approach to silicon test and debug. Built on the foundation of the best-in-class test tools for each test discipline, Tessent brings these solutions together in a powerful test flow and hierarchical architecture that ensures total chip coverage, including logic, memory, mixed-signal and I/O. The flexibility of the Tessent product line enables the highest quality test technology to be applied throughout the product lifecycle—from wafer and package test, burn-in, to in-system and field test.
What You Will Learn
In this seminar you will come away with a thorough understanding of the Tessent® embedded test flow and will be able to return to your work environment prepared to implement Tessent Memory BIST in your designs.
- Hierarchical Logic Test
- Memory test and self-repair
- High-Speed I/O test
- Reduced pin count test
- Power-aware test
- Interactive Bring-up
Plug-and-Play Test Strategy for 3D ICs
As the industry transitions to 3D ICs, new test strategies are being developed to meet to two 3D IC test goals: improving the pre-packaged test quality and establishing new tests between the stacked die....
Tessent Product Suite Overview
Built on the foundation of the best-in-class test tools for each test discipline, Tessent® brings these solutions together in a powerful test platform that ensures total chip coverage.