Mentor.com :: Silicon Test and Yield Analysis Resources

White Paper: Ready for 3D-IC

Thu, 19 Jan 2012 08:00:00 GMT

This technical presentation describes the challenges and Mentor's solutions for verifying and testing IC designs targeted for 3D packages, such as stacked die using TSVs or multi-die packages using silicon interposers.

Industry Article:Semiconductor yield improvement with scan diagnosis

Wed, 16 Nov 2011 08:00:00 GMT

Energy Vs. Power: Energy, Power Optimization Is A System-Level Challenge

News Article:Mentor Graphics Receives TSMC’s Partner of the Year Award for 3D-IC Design Enablement

Fri, 11 Nov 2011 14:00:00 GMT

WILSONVILLE, Ore., November 11, 2011—Mentor Graphics Corporation (NASDAQ: MENT) today announced it was chosen as a TSMC 2011 Partner of the Year for its role in 3D-IC design enablement. The Mentor® and TSMC collaborations provide a robust flow for verifying multi-die system designs using silicon interposer integration techniques.

Industry Article:Diagnosis-Driven Yield Analysis Improves Mature Yield

Mon, 07 Nov 2011 08:00:00 GMT

News Article:Mentor Graphics Announces Completion of 20 nm Test Chip Tapeout with STMicroelectronics Using Olympus-SoC Place and Route System

Fri, 04 Nov 2011 13:00:00 GMT

WILSONVILLE, Ore., November 4, 2011—Mentor Graphics Corporation (NASDAQ: MENT) today announced the successful tapeout of a 20 nm test chip in collaboration with STMicroelectronics, marking a significant milestone in the development of a complete Mentor® design-to-silicon solution for next-generation process technology. The test chip was implemented using the Olympus-SoC™ place and route system, and verified using the Calibre® nmDRC platform, which is the verification and double patterning solution used by R&D teams at STMicroelectronics. Together, the Olympus-SoC, Calibre and Tessent® silicon test and yield analysis products provide a comprehensive flow for 20 nm IC development.

Industry Article:Direct diagnosis for compressed ATPG patterns: A successful industrial experiment with layout-aware diagnosis

Wed, 19 Oct 2011 07:00:00 GMT

Technology Overview:Mentor Graphics support of ARM IP

Tue, 18 Oct 2011 18:07:00 GMT

This video is an overview of the partnership between ARM® and Tessent®, Mentor Graphics silicon test solutions product group. Tessent and ARM co-developed support for the ARM shared bus where MemoryBIST controllers reside outside of the ARM core, and utilize the shared bus to test the memory inside the core. Tessent and ARM also co-developed the "Mentor reference flow for ARM architecture" flow, available from Mentor Graphics. This provides a reusable, customizable, repeatable flow for customers using Tessent TestKompress® and ARM processor IP.

Technology Overview:3D IC Test

Tue, 18 Oct 2011 18:07:00 GMT

3D-IC technology has been getting a lot of attention in the press and at technical conferences. Whether the 3D-IC is built on Silicon Interposers or stacked die with Through Silicon Vias, Mentor Graphics is uniquely positioned to support our customers with both the Calibre and Tessent product lines.

Technology Overview:Tessent Product Suite Overview

Tue, 18 Oct 2011 18:07:00 GMT

Built on the foundation of the best-in-class test tools for each test discipline, Tessent® brings these solutions together in a powerful test platform that ensures total chip coverage.

Technology Overview:DFM-Aware Yield Analysis

Tue, 18 Oct 2011 18:07:00 GMT

This video provides an overview of the Mentor Graphics® DFM-Aware Yield Analysis. Based on Calibre® YieldAnalyzer®, Tessent Diagnosis, and Tessent YieldInsight® customers are able to identify DFM rules that best describe the design-process induced systematic defects. Resolving design-process induced systematic defects is one of the few ways that fabless semiconductor companies can directly improve their yield.