IEEE Conference Papers
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A Guide to Power-Aware Memory RepairLearn more about an effective memory repair methodology. Featured Papers
2011 Papers
2011 Papers
ITC 2011
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Low-Power Compression Utilizing Clock Gating
E.K. Moghaddam, S.M. Reddy, University of Iowa * J. Rajski, Mentor Graphics -
Cell-aware Analysis for Small-Delay Effects and Production Test Results from Different Fault Models
F. Hapke, J. Schloeffel, W. Redemund, A. Glowatz, J. Rajski, Mentor Graphics * M. Reese, J. Rearick, J. Rivers, AMD -
Adaptive Parametric BIST of HighSpeed Parallel I/Os via Standard Boundary Scan
S. Sunter, A. Roy, Mentor Graphics -
EDT Channel Bandwidth Management in SOC Designs with Pattern-independent Test Access Mechanism
J. Tyszer, J. Janicki, Poznan University of Technology; A. Dutta, M. Kassab, G. Mrugalski, N. Mukherjee, J. Rajski, Mentor Graphics -
A Novel Test Access Mechanism for Failure Diagnosis of Multiple Isolated Identical Cores
M. Sharma, A. Dutta, W-T. Cheng, B. Benware, M. Kassab, Mentor Graphics -
Deterministic IDDQ Diagnosis Using a Net-Activation-based Model
A. Kun, R. Arnold, P. Heinrich, G. Maugard, Infineon Technologies; H. Tang, W. Cheng, Mentor Graphics
ISTFA 2011
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Layout-Aware Diagnosis Leads to Efficient and Effective Physical Failure Analysis
Manish Sharma, Sergej Schwarz, Juergen Schmerberg, Kathy Yang, Ting-Pu Tai, Mentor Graphics, Yuan-Shih Chen,
Cheng-Yiing Chuang, Feng-Ming Kuo, TSMC, Mike Brennan, James Yeh, and Alan Ma, AMD -
Device Selection for Failure Analysis of Chain Fails Using Diagnosis Driven Yield Analysis
Chris Schuermyer, Brady Benware, Graham Rhodes, Davide Appello,
Vincenzo Tancorre, Olivia Riewer, STMicroelectronics -
Diagnose Compound Hold Time Faults Caused by Spot Delay Defects at Clock Tree
Yu Huang, Wu-Tung Cheng, Ting-Pu Tai, Liyang Lai, Ruifeng Guo, Mentor Graphics,
Feng-Ming Kuo, Yuan-Shih Chen, TSMC
2010 Papers
2010 Papers
IEEE Conference PapersCopyright © 2010 IEEE
ITC 2010
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BIST of I/O Circuit Parameters via Standard Boundary Scan
Stephen Sunter, Mentor Graphics, Matthias Tilmann, Renesas Electronics Europe GmbH -
Clock Control Architecture and ATPG for Reducing Pattern Count in SoC Designs with Multiple Clock Domains
Tom Waayers, Richard Morren, NXP, Xijiang Lin, Mark Kassab, Mentor Graphics -
Test Cycle Power Optimization for Scan-based Designs
Kun-Han Tsai, Yu Huang, Wu-Tung Cheng, Ting-Pu Tai, Mentor Graphics, Augusli Kifli, Faraday Technology Co. -
Dynamic Channel Allocation for Higher EDT Compression in SoC Designs
M. Kassab, G. Mrugalski, N. Mukherjee, J. Rajski, Mentor Graphics, J. Janicki, J. Tyszer, Pozan University of Technology -
Defect-Oriented Cell-Internal Testing
F.Hapke, R.Krenz-Baath, A.Glowatz, J.Schloeffel, W.Redemund, M.Wittke, Mentor Graphics, H.Hashempour, S.Eichenberger, NXP Semiconductors -
Experiences with Parametric BIST for Production Testing PLLs with Picosecond Precision
Rakesh Kinger, Swetha Narasimhawsamy Broadcom Corp., Stephen Sunter, Mentor Graphics -
Low Power Compression of Incompatible Test Cube
D. Czysz, G. Mrugalski, N. Mukherjee, J. Rajski, Mentor Graphics, P. Szczerbicki, J. Tyszer, Poznan University of Technology -
Low Capture Power At-Speed Test in EDT Environment
Elham Moghaddam, S. M. Reddy, U. Iowa, Janusz Rajski, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab, Mentor Graphics
2009 Papers
2009 Papers
IEEE Conference PapersCopyright © 2009 IEEE and Copyright © 2009 ASM International® All Rights Reserved.
ATS
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At-Speed Scan Test Method for the Timing Optimization and Calibration
H Tsai, R Guo, W T Cheng, Mentor Graphics -
N-Distinguishing Tests for Enhanced Defect Diagnosis
J Rajski, G Chen, Mentor Graphics, S Reddy, Univ of Iowa, I Pomeranz, Purdue -
On Improving Diagnostic Test Generation for Scan Chain Failures
X Tang, R Guo, W T Cheng, Y Huang, Mentor Graphics, S Reddy, Univ of Iowa -
Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns
Y Huang, W T Cheng, R Guo, TP Tai, Mentor Graphics, F M Kuo, Y S Chen, TSMC -
Scan Compression Implementation in Industrial Design – Case Study
D Hsu, Ralink, R Press, Mentor Graphics -
Test Generation with On-Chip Clock Generators
X Lin, M Kassab
ETS
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Improving Diagnostic Test Generation for Scan Chain Failures Using Multi-Cycle Scan Patterns
X Tang, R Guo, W T Cheng, Y Huang, Mentor Graphics, S Reddy, Univ of Iowa -
Speed-Path Debug Using At-Speed Scan Test Patterns
R Guo, W T Cheng, H Tsai, Mentor Graphics
ITC
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Compression Based on Deterministic Vector Clustering of Incompatible Test Cubes
G. Mrugalski, N. Mukherjee, J. Rajski D. Czysz, Mentor Graphics, J. Tyszer, Poznan University of Technology -
Defect-Oriented Cell-Aware ATPG and Fault Simulation for Industrial Cell Libraries and Designs
F.Hapke, R.Krenz-Baath, A.Glowatz, J.Schloeffel, Mentor Graphics, H.Hashempour, S.Eichenberger, C.Hora, D. Adolfsson, NXP Semiconductors -
Fault Diagnosis for Embedded Read-Only Memories
N. Mukherjee, A. Pogiel, J. Rajski, Mentor Graphics, J. Tyszer, Poznan University of Technology -
Running scan test on three pins: yes we can!
J. Moreau, T. Droniou, P. Lebourg, P. Armagnat, STMicroelelectronics, Reprinted with permission of STMicroelectronics and IEEE -
Test Point Insertion Using Functional Flip-Flops to Drive Control Points
Joon-Sung Yang, Nur A. Touba, University of Texas, Austin, Benoit Nadeau-Dostie, Mentor Graphics -
Testing Bridges to Nowhere - Combining Boundary Scan and Capacitive Sensing
Stephen Sunter, Mentor Graphics, Kenneth P. Parker, Agilent Technologies
2008 Papers
2008 Papers
Copyright © 2008 IEEE and Copyright © 2008 ASM International® All Rights Reserved.
ITC
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Efficiently Performing Yield Enhancements by Identifying Dominant Physical Root Cause from Test Fail Data
M Sharma, B Benware, L Ling, D Abercrombie, L Lee, M Keim, H Tang, WT Cheng and TP Tai, Mentor Graphics, YJ Chang, R Lin, UMC, A Man, AMD -
High Throughput diagnosis via Compression of Failure Data in Embedded Memory BIST
N Mukherjee, J Rajski, Mentor Graphics, A Pogiel, J Tyszer, Pozan University of Technology -
Low Power Scan Shift and Capture in the EDT Environment
M Kassab, X Lin, G Mrugalski, J Rajski, Mentor Graphics, D Czysz, J Tyszer, Poznan University of Technology -
Test Generation for Interconnect Opens
X Lin, J Rajski, Mentor Graphics
ISTFA
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Timing Failure Debug using Debug-Friendly Scan Patterns and TRE
C Burmer, Infineon, R Guo, WT Cheng, X Lin, B Benware, Mentor Graphics, -
Improving Fault Isolation using Iterative Diagnosis
K Gearhardt, LSI, C Schuermyer, R Guo, Mentor Graphics
Archived Papers
2007 Papers
2007 Papers
Copyright © 2008 IEEE. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Mentor Graphics's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org.
SemiCon 2007
- DFT Approaches Enable Mass Production Test
R Press, T Kobayashi, Mentor Graphics
ITC 2007
- Effects of Embedded Decompression and Compaction Architectures on Side-Channel Attack Resistance
Chunsheng Liu, Yu Huang - Diagnose Compound Scan Chain and System Logic Defects
Y.Huang, WT Cheng, R.Guo, Mentor Graphics, W.Hsu, YS Chen, TSMC and A.Man, AMD - Dynamic N-Detect Patterns Based on Equivalent Faults
P.Reuter, Y.Huang, Mentor Graphics - Enhanced Testing of Clock Faults
T.McLaurin, R.Slobodnik, ARM, KH Tsai, A.Keim, Mentor Graphics - Faster Defect Localization in Nanometer Technology based on Defective Cell Diagnosis
M.Sharma, WT Cheng, TP Tai, Mentor Graphics, YS Cheng, W.Hsu, TSMC, C.Liu and S.Reddy, University of Iowa, and A.Man, AMD - Interconnect Open Defect Diagnosis with Minimal Physical Information
C.Liu, S.Reddy, Univeristy of Iowa, W.Zou, WT Cheng, M.Sharma, H.Tang, Mentor Graphics
ATS 2007
- Effect of IR-Drop on Path Delay Tsting Using Statistical Analysis
C.Liu, Y.Wu, University of Nebraska-Lincoln, and Y.Huang, Mentor Graphics - Fault Dictionary Based Scan Chain Failure Diagnosis
R.Guo, Y.Huang, WT Cheng, Mentor Graphics - Improving Performance of Effect-Cause Diagnosis with Minimal Memory Overhead
C.Liu, S. Reddy, University of Iowa, H.Tang, WT Cheng, W.Zou, Mentor Graphics - Programmable Logic BIST for At-speed Test
Y.Huang, X.Lin, Mentor Graphics - Test Generation for Timing-Critical Transition Faults
X.Lin, M.Kassab, J.Rajski, Mentor Graphics
VTS 2007
- Effects of Embedded Decompression and Compaction Architectures on Side-Channel Attack Resistance
C Liu, Univ of Nebraska, Y Huang, Mentor Graphics
2006 Papers
2006 Papers
IEEE Conference PapersCopyright © 2006
ITC
- Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement
H.Tang, S.Manish, J.Rajski, M.Keim, B.Benware - Test Smorgasbord: Analog Boundary-Scan Description Language (ABSDL) for Mixed-Signal Board Test
B. Suparjo, Mentor Graphics, A. Ley, ASSET InterTech, H. Ehrenberg, GOEPEL Electronics - Production Test Concerns: A Rapid Yield-Learning Flow Based on Production-Integrated Layoutaware Diagnosis
M. Keim, N. Tamarapalli, H. Tang, M. Sharma, J. Rajski, Mentor Graphics, C. Schuermyer, B. Benware, LSI Logic - Quality Issues in Transition-Fault Testing: Improving Transition-Fault Test Pattern Quality Through At-Speed Diagnosis
N. Tendolkar, D. Belete, B. Schwarz, B. Podnar, S. Karako, Freescale Semiconductor, A. Gupta, The University of Texas at Austin, W. Cheng, A. Babin, K. Tsai, N. Tamarapalli, G. Aldrich, Mentor Graphics - Advanced Diagnosis: Combined Electrical and Physical - Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology
V. Mehta, M. Marek-Sadowska, University of California, Santa Barbara; K-H. Tsai, J. Rajski, Mentor Graphics - Data Compression Methodology and Modeling: X-Press Compactor for 1000x Reduction of Test Data
G. Mrugalski, J. Rajski, WT. Cheng, N. Mukherjee, Mentor Graphics; J. Tyszer, Poznan University of Technology - Compression Diagnostics: Signature-based Diagnosis for Logic BIST
M. Sharma, W. Cheng, T. Rinderknecht, L. Lai, C. Hill, Mentor Graphics - Diagnosis Improvement: Diagnosis with Limited Failure Information
Y. Huang, W. Cheng, N. Tamarapalli, J. Rajski, R. Klingenberg, Mentor Graphics - Test Power Reduction: Preferred Fill: A Scalable Method to Reduce Capture Power for Scanbased Designs
X. Lin, J. Rajski, Mentor Graphics; S. Remersaro, S. Reddy, University of Iowa; I. Pomeranz, Purdue University
2005 Papers
2005 Papers
IEEE Conference PapersCopyright © 2005
ITC
- Compressed Pattern Diagnosis For Scan Chain Failures
Y.Huang, W-T.Cheng, J.Rajski - Compression Mode Diagnosis Enables High Volume Volume Monitoring Diagnosis Flow
A.Leininger, P.Muhmenthaler, W-T Cheng, N.Tamarapalli, W.Yang, H.Tsai - Full-Speed Field-Programmable Memory BIST Architecture
X.Du, N.Mukherjee, W-T Cheng, S.Reddy - Chasing Subtle Embedded RAM Defects for Nanometer Technologies
T.Powell, A.Kumar, J.Rayhawk, N.Mukherjee - X-filter: Filtering unknowns from compacted test responses
M.Sharma, W-T Cheng - Built-In Constraint Resolution
G.Giles, J.Irby, D.Toneva, K.H.Tsai
ISTFA
- Advanced Scan Diagnosis Based Fault Isolation and Defect Identification for Yield Learning
C.Eddleman, N.Tamarapalli, W-T Cheng
ITSW
- Logic BIST Diagnostics Using Simple Synchronised MISR Unload
Chris Hill and Thomas Rinderknecht, Mentor Graphics
In this paper we present a conmercial logic BIST diagnostic approach; using an enhanced BIST controller that supports simple synchronised observation of the MISR on a per pattern basis, reinitialising the BIST controller. Selected patterns are unloaded and diagnostic inference identifies candidate faults and their locations. The approach is flexible and can be tailored to fit constraints of the test environment. At-speed BIST is supported, as is diagnostics through a low speed interface, such as IEEE 1149.1.
2004 Papers
2004 Papers
IEEE Conference PapersCopyright © 2004
ITC
- ATE Data Collection - A Comprehensive Requirements Proposal to Maximize ROI of Test
M. Rehani, R. Madge, J. Teisher, LSI Logic; D.Abercrombie, Mentor Graphics; J. Saw, Invantest - Realizing High Test Quality Goals with Smart Test Resource Usage
X. Gu, C. Wang, A. Lee, B. Eklow, Cisco Systems; K. Tsai, J. Tofte, M. Kassab, J. Rajski, Mentor Graphics - Hierarchical DFT Methodology: A Case Study
J. Remmers, Plexus Design Solutions; R.Fisette, Mentor Graphics
2003 Papers
2003 Papers
IEEE Conference PapersCopyright © 2003
2003 Conference Papers
- Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault,
Yu Huang, Wu-Tung Cheng, Mentor Graphics Corporation, Sudhakar M. Reddy, University of Iowa, Cheng-Ju Hsieh, Yu-Ting Hung, Faraday Technology Corporation - Convolutional Compaction of Test Responses,
Janusz Rajski, Chen Wang, Mentor Graphics Corporation, Jerzy Tyszer, Pozan University of Technology, Sudhakar M. Reddy, University of Iowa ECE Department - Impact of Multiple-Detect Test Patterns on Product Quality,
Brady Benware, Chris Schuermyer, Sreenevasan Ranganathan, Robert Madge, Prabhu Krishnamurthy LSI Logic Corporation, Nagesh Tamarapalli, Kun-Han Tsai, Janusz Rajski, Mentor Graphics Corporation