Silicon Test and Yield Analysis
Mentor delivers highest quality silicon test and failure analysis tools to ensure that each device produced will be free of defects before delivery. Effective test development tools achieve these quality targets while maintaining profitability with lower test costs.
Industry Leading Scan Test Tools
TestKompress® is part of the Mentor Graphics industry and technology-leading tool suite that delivers the highest quality scan test with the lowest manufacturing test cost. The tool suite comprises solutions for:
- Scan insertion
- Automatic test pattern generation (ATPG)
- On-chip compression
- Memory built-in self-test (BIST)
- Logic BIST
- Boundary scan insertion
High Quality Test Drives Yield and Failure Analysis
YieldAssist™ is an advanced scan test diagnosis tool that performs accurate and high-resolution diagnosis using tester failure data, design netlists, and layout data. YieldAssist is the solution for:
- Effectively identifying root cause of manufacturing test failures
- Enabling Diagnosis-Driven yield analysis
- Accelerating failure analysis with high-volume online diagnosis
Solutions
Silicon Test Solutions
Mentor Graphics provides a complete set of tools for developing test for logic and embedded memory.
Memory Test Solutions
Typically, more than half of a chip’s functional area consists of memory arrays. Thorough testing of these arrays is essential for ensuring high product quality. Memory built-in self-test (MBIST) is the most effective method for thoroughly testing each memory.
Yield Analysis Solutions
Mentor Graphics provides diagnostic-driven yield analysis tools to analyze failing devices.
Techpubs and Resources
Silicon Test & Yield Analysis Techpubs
At-Speed and Advanced Fault Models for Achieving High Quality Test
techpub: With the increasing clock speeds and the decreasing feature sizes found in today's nanometer designs, at-speed testing is a requirement to achieve high quality test results. In addition, new advanced fault... View Techpub
Combining Compression with Fewer Pins Dramatically Saves I/O during Multi-Site Test
techpub: The manufacturing test process for ICs is increasing in cost and effort to keep up with rigorous quality standards, complexity of newer designs and process nodes, narrower time-to-market windows, and demand... View Techpub
High Quality Test Solutions for Secure Applications
techpub: Designs for secure applications such as smart cards and those used in the defense industry require security to ensure sensitive data is inaccessible to outside agents. Conversely, scan chains have been... View Techpub
Faster Root Cause Analysis with YieldAssist - Presentation and Demo
On-demand Web SeminarAt the advanced design nodes now being manufactured, the ramp to expected yield is taking longer causing increased cycle times and reduced profits. This presentation discusses how using YieldAssist and... View Video
Yield Ramp
Diagnosis-driven yield analysis can rapidly identify probable cause of failures, enabling you to implement corrective actions in the manufacturing process or make changes to the design. Accurate diagnosis allows you to accelerate yield ramp during initial production and improve expected yields for mature products, speeding your time to market and increasing profitability.
Learn more
News & Press
- UMC Qualifies Comprehensive Mentor Graphics Silicon Test Suite for its 65nm and 40nm IC Reference Flows
- Mentor Graphics and LogicVision Sign Definitive Merger Agreement
- Mentor Graphics TestKompress ATPG Software Wins Test & Measurement World’s Test of Time Award
- Mentor and NXP Achieve Major Milestone in Silicon Test Partnership
- More