Silicon Test and Yield Analysis
The Tessent® Product Suite
Tessent combines features of deterministic scan testing, embedded pattern compression, built-in self test, specialized embedded memory test and repair, and boundary scan, as well as board and system-level test technologies.
The Tessent product suite provides comprehensive silicon test and yield analysis solutions that address the challenges of manufacturing test, debug, and yield ramp for today’s SoCs. Built on the foundation of the best-in-class solutions for each test discipline, Tessent brings them together in a powerful test flow that ensures total chip coverage.
EDACafe Interview with Steve Pateras at DAC 2011: 3D TSV and Silicon Test
Tessent Silicon Test & Yield Analysis Solution
Logic Test
Mentor Graphics offers the industry’s most powerful suite of logic test solutions with more than a decade, and thousands of tape-outs, of successful high-quality test using both compression and vectorless approaches.
Memory Test
Tessent® memory test solutions include comprehensive test and diagnostic capabilities to address the quality requirements of new process nodes and memory designs as well as comprehensive repair analysis and self-repair capabilities.
Mixed-Signal Test
The Tessent® mixed-signal test solutions are vendor- and ATE-independent, addressing the growing number of SerDes interfaces and PLLs on today’s SoC designs.
Silicon Learning
The Tessent® silicon learning products increase productivity during critical silicon validation and yield ramp phases, providing solutions for test bring-up, silicon characterization, diagnosis-driven yield analysis, and failure analysis.
White Papers
Ready for 3D-IC
This technical presentation describes the challenges and Mentor's solutions for verifying and testing IC designs targeted for 3D packages, such as stacked die using TSVs or multi-die packages using silicon... View White Paper
Low Power Test
Today’s advanced integrated circuit (IC) designs are increasing in complexity, with their seemingly endless progression to smaller geometries, ever increasing integration between analog and digital... View White Paper
User Defined Fault Models
This white paper describes the functionality of user defined fault models (UDFM), including gate exhaustive UDFM and cell-aware UDFM, and the effectiveness of lowering DPM in devices. View White Paper
Multimedia
Tessent Product Suite Overview
Built on the foundation of the best-in-class test tools for each test discipline, Tessent® brings these solutions together in a powerful test platform that ensures total chip coverage. View Technology Overview
User-Defined Fault Models
Mentor Graphics recognizes their customer's need for quickly developing unique fault models to address new manufacturing defects and has introduced user-defined fault models (UDFM) as an enhancement to... View Technology Overview
Mentor Graphics support of ARM IP
This video is an overview of the partnership between ARM® and Tessent®, Mentor Graphics silicon test solutions product group. Tessent and ARM co-developed support for the ARM shared bus where MemoryBIST... View Technology Overview
News and Press
- Mentor Graphics Receives TSMC’s Partner of the Year Award for 3D-IC Design Enablement (Nov 11, 2011)
- Mentor Graphics Announces Completion of 20 nm Test Chip Tapeout with STMicroelectronics Using Olympus-SoC Place and Route System (Nov 4, 2011)
- Mentor Graphics Adds User Defined Fault Models and Cell-Aware ATPG to Improve IC Test Quality (Sep 19, 2011)
- ARM and Mentor Graphics Define Comprehensive Test Methodology for ARM-based Designs (Sep 19, 2011)