Logic Test
Advanced design techniques are used in creating the logic portions of SoCs, presenting significant challenges to achieving high-quality silicon test. To meet these challenges, Mentor Graphics offers the industry’s most powerful suite of logic test solutions.
These solutions have more than a decade, and thousands of tape-outs, of successful high-quality test using both compression and vectorless approaches. Together, they provide maximum flexibility for achieving the most effective test time versus quality optimization.
The Tessent® logic test solutions also provide unique support for reduced pin count testing, extensive support for testing low-power designs as well as advanced fault models like Cell-Aware.
Avago Technologies and Mentor Graphics: Test Challenges and Solutions
Products
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Tessent TestKompress
Tessent® TestKompress® is the industry-leading ATPG tool that provides the highest quality scan test with the absolute lowest test cost. TestKompress has an industry-proven ATPG engine that applies effective fault models to the entire logic design. Manufacturing test costs are held in check by an award-winning test pattern compression technique called Embedded Deterministic Test (EDT).
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Tessent LogicBIST
Tessent® LogicBIST is the industry’s leading built-in self-test solution for testing the digital logic components of integrated circuits. It includes unique features targeted at nanometer SoC designs that reduce test costs and shorten time-to-market while maximizing test quality.
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Tessent SoCScan
Tessent® SoCScan complements the Mentor Graphics ATPG solutions, Tessent TestKompress and Tessent FastScan, by providing an environment to insert a hierarchical scan and clock control infrastructure for at-speed testing and effective test reuse.
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Tessent FastScan
Tessent® FastScan™ is an ATPG solution with a wide range of fault models, comprehensive design rules checks, extensive clocking support, and innovative algorithms for performance-oriented pattern compaction, making it the most versatile ATPG tool available.
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Tessent BoundaryScan
Tessent® BoundaryScan automates adding IEEE 1149.1 standard boundary scan support to ICs of any size or complexity. The boundary scan logic can be accessed throughout the life of the IC, including manufacturing test at all package levels, silicon debug, and system verification.
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Tessent IJTAG
Tessent ® IJTAG provides automation to support the emerging IEEE P1687 standard for plug-and-play IP integration. Tessent IJTAG simplifies the process of connecting any number of IEEE P1687 compliant IP blocks into an integrated, hierarchical network and to communicate commands to the blocks from a single access point. It can be used by IP providers to ensure compliance to the standard as well as by chip designers and test engineers to integrate 1687 compliant IP from various sources into their designs and operate them effectively.
Technology Overview
The combination of compression and logic BIST provides the test techniques needed generate the highest quality test. Learn how these techniques, integrated using a common hierarchical SoC flow, provide...
Datasheets
Toolbox
Tessent Training
We have training courses available for Tessent products in our training centers around the world, online, or at your site.
Contact Mentor Graphics
- Request Information or call toll free: 1-800-547-3000
Mentor Technology Speaker Series
Janusz Rajski, Ph.D.
View this online Speaker Series to hear Janusz Rajski, Ph.D, Director of Engineering, Mentor Graphics, speak on the last 30 years of test and testability and how the complexity of scan test has evolved. Learn about embedded deterministic test and how EDT technology has revolutionized manufacturing test with the implementation of TestKompress®. View Today!