Logic Test

Advanced design techniques are used in creating the logic portions of SoCs, presenting significant challenges to achieving high-quality silicon test. To meet these challenges, Mentor Graphics offers the industry’s most powerful suite of logic test solutions.

These solutions have more than a decade, and thousands of tape-outs, of successful high-quality test using both compression and vectorless approaches. Together, they provide maximum flexibility for achieving the most effective test time versus quality optimization.

The Tessent® logic test solutions also provide unique support for reduced pin count testing as well as extensive support for testing low-power designs.

Avago Technologies and Mentor Graphics: Test Challenges and Solutions

Jason Brown, World Wide Test Manager, Avago Technologies, and Jay Jahangiri, Technical Marketing Engineer, Mentor Graphics, speak about silicon test challenges and solutions. View Video

Products

• Tessent TestKompress

  Tessent® TestKompress® is the industry-leading ATPG tool that provides the highest quality scan test with the absolute lowest test cost. TestKompress has an industry-proven ATPG engine that applies effective fault models to the entire logic design. Manufacturing test costs are held in check by an award-winning test pattern compression technique called Embedded Deterministic Test (EDT).

• Tessent LogicBIST

  Tessent® LogicBIST is the industry’s leading built-in self-test solution for testing the digital logic components of integrated circuits. It includes unique features targeted at nanometer SoC designs that reduce test costs and shorten time-to-market while maximizing test quality.

• Tessent SoCScan

  Tessent® SoCScan complements the Mentor Graphics ATPG solutions, Tessent TestKompress and Tessent FastScan, by providing an environment to insert a hierarchical scan and clock control infrastructure for at-speed testing and effective test reuse.

• Tessent FastScan

  Tessent® FastScan™ is an ATPG solution with a wide range of fault models, comprehensive design rules checks, extensive clocking support, and innovative algorithms for performance-oriented pattern compaction, making it the most versatile ATPG tool available.

• Tessent BoundaryScan

  Tessent® BoundaryScan automates adding IEEE 1149.1 standard boundary scan support to ICs of any size or complexity. The boundary scan logic can be accessed throughout the life of the IC, including manufacturing test at all package levels, silicon debug, and system verification.

Technology Overview

Bringing Compression and BIST Technologies Together

The combination of compression and logic BIST provides the test techniques needed generate the highest quality test. Learn how these techniques, integrated using a common hierarchical SoC flow, provide the highest defect coverage while reducing overall test time.

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Bringing Compression and BIST Technologies Together

Technology Overview

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