Advanced design techniques are used in creating the logic portions of SoCs, presenting significant challenges to achieving high-quality silicon test. To meet these challenges, Mentor Graphics offers the industry’s most powerful suite of logic test solutions.
These solutions have more than a decade, and thousands of tape-outs, of successful high-quality test using both compression and vectorless approaches. Together, they provide maximum flexibility for achieving the most effective test time versus quality optimization.
The Tessent® logic test solutions also provide unique support for reduced pin count testing, extensive support for testing low-power designs as well as advanced fault models like Cell-Aware.
Mentor Technology Speaker Series
View this online Speaker Series to hear Janusz Rajski, Ph.D, Director of Engineering, Mentor Graphics, speak on the last 30 years of test and testability and how the complexity of scan test has evolved. Learn about embedded deterministic test and how EDT technology has revolutionized manufacturing test with the implementation of TestKompress®. View Today!
Mentor Graphics Tessent® BoundaryScan automates adding IEEE 1149.1 standard boundary scan support to ICs of any size or complexity. The boundary scan logic can be accessed throughout the life of the...
Tessent® FastScan™ is an ATPG solution with a wide range of fault models, comprehensive design rules checks, extensive clocking support, and innovative algorithms for performance-oriented pattern...
Mentor Graphics Tessent® LogicBIST is the industry’s leading built-in self-test solution for testing the digital logic components of integrated circuits. It includes unique features targeted at...
Tessent® Scan™ inserts scan test structure into a netlist, delivering design that is completely ready for scan testing and pattern compression.