TestKompress

TestKompress® is the industry-leading automatic test pattern generation (ATPG) tool that delivers the highest quality scan test with the lowest manufacuturing test cost. The foundation of TestKompress is the industry-proven ATPG engine that is able to apply all the fault models necessary for thorough silicon test. TestKompress uses a patented on-chip compression technique to create scan pattern sets that have dramatically less test data volume and reduced test time on the automatic test equipment.

Features and Benefits

  • Employs patented Embedded Deterministic Test (EDT™) technology
  • Provides up to a 100X reduction in test data volume and test time
  • Supports all ATPG fault models and pattern types, including stuck-at, IDDQ, transition and path-delay for at-speed test
  • EDT Logic can be generated in all design flows
  • Fits into any scan-based design flow
  • Supports accurate at-speed clock edges and both launch-off-shift and capture transition fault application
  • Named capture procedures provide support of the generation of accurate at-speed clock pulses with on-chip PLL
  • Uses scan/ATPG methodology. Fully compatible with industry design flows and Mentor’s entire suite of tools
  • The ATPG Expert ™ feature automates the creation of optimal test pattern results
  • DFTVisualizer is integrated within TestKompress for design viewing and correcting testability problems

Datasheet

ToolBox