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The Tessent™ mixed-signal test solutions are vendor- and ATE-independent, addressing the growing number of SerDes interfaces and PLLs on today’s SoC designs. Characterization with PC plus GPIB-controlled benchtop equipment reduces tester hardware requirements, and the microWire-controlled clock conditioner PLL shortens your time-to-market. Tessent SerdesTest and Tessent PLLTest minimize tester hardware requirements and reduce tests costs.


Tessent SerdesTest

Mentor Graphics Tessent SerdesTest provides complete, parametric, embedded test for multi-Gb/s SerDes. View Product Overview

Tessent PLLTest

Mentor Graphics Tessent PLLTest provides complete, parametric, embedded test for PLLs, DLLs, and clock signals. View Product Overview

Tessent BoundaryScan

Mentor Graphics Tessent® BoundaryScan automates adding IEEE 1149.1 standard boundary scan support to ICs of any size or complexity. The boundary scan logic can be accessed throughout the life of the... View Product Overview

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