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The Next Big Thing Towards Increasing Automotive Semiconductor Test Quality



The growing amount of electronics within today’s automobiles is driving very high quality and reliability requirements to a widening range of semiconductor devices. Improvements in test solutions are needed not only to maintain very high quality levels in more advanced technology nodes but to also address increasing reliability requirements such as defined within the ISO 26262 standard. This seminar summarizes the latest approaches in testing automotive semiconductors. It covers, among others, solutions around IEEE to deterministically target the increasing number of digital and mixed-signal embedded IP, as well as a new hybrid ATPG compression and logic BIST solution that provides more efficient defect coverage together with the ability to apply tests within the system for long-term reliability. This hybrid solution also supports a new cell-aware test generation approach, which is the focus of this seminar.

It is well known that traditional fault models and associated test patterns are becoming increasingly less effective at achieving desired silicon quality levels. The cell-aware test methodology which models and targets defects within each cell addresses these inherent limitations of traditional testing. It has been shown to significantly reduce DPM levels in shipped devices. This seminar will cover all aspects of this exciting new test methodology. Details of the underlying technology will be reviewed as well as a description of the cell library characterization flow necessary for creating new cell-aware fault models. Pattern and coverage results for several industrial designs will be presented as well as silicon test results gathered over several million parts. Cell-internal diagnosis and physical failure analysis results will be presented confirming that cell-aware tests detect real physical defects.

What You Will Learn

You will receive an update on the latest advances in testing modern semiconductors, especially for the automotive market. You will gain an understanding of the theory behind the cell-aware test methodology and the flows necessary to create cell-aware fault models. More importantly you will learn how this new methodology can significantly improve the quality of your parts and ultimately help improve yield as your organization moves to new technology nodes or plans to improves the current node.

About the Presenter

Presenter Image Martin Keim

Dr. Martin Keim joined the Silicon Test Solutions group of Mentor Graphics in 2001, where he is currently a senior technical marketing engineer and marketing lead for Mentor’s IJTAG products. Previously, he was a Test Engineer with Infineon Technologies in Munich, Germany. For several years, he has worked on the organizing committee of the International Symposium for Testing and Failure Analysis (ISTFA), and he is an active member of the IEEE working group. Dr. Keim was editor of the sixth edition of the Microelectronics Failure Analysis Desk Reference Manual and was responsible for the test and diagnosis chapters. He holds several national and international patents and is author of many technical publications. He received a doctorate in informatics from the Albert-Ludwigs University, Germany.

Who Should View

  • Engineering managers responsible for manufacturing test costs and outgoing product quality levels.
  • DFT and test engineers responsible for the generation and/or application of manufacturing test patterns.
  • Product and test engineers responsible for the diagnosis of semiconductor failures.
  • Engineers responsible for the generation and maintenance of cell libraries

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