The Defect-Free & High Yield DFT Solution for ARM IP
On-demand Web Seminar
Tessent Support of ARM Cores and Memories
Mentor Graphics and ARM are partnering to provide customers with tools to deliver the most advanced, defect free and highest yielding IC products to market in a timely manner. The two companies continue to work to ensure Mentor’s Tessent family of silicon test products are optimized to provide comprehensive and cost-effective test coverage of ARM processors and memory IP.
What You Will Learn
This seminar will describe the specific test solutions developed to cover both the memory and logic test requirements of ARM-based designs. Special emphasis will be placed on recent enhancements to these solutions including improvements to the automated support of the ARM standardized MBIST (aka Shared Bus) interface. This interface enables test access to memories through the functional path, resulting in higher quality test and reduced impact on performance. The interface however requires that all of the memories attached to that interface be tested sequentially. For large memories such as L2 caches this may cause excessive test time. A new method developed by ARM to add multiple interfaces internal to the core to add flexibility to the current solution will be presented.
About the Presenters
Stephen Pateras is a product marketing director at Mentor Graphics. His previous position was VP Marketing at LogicVision. While at LogicVision Stephen also held senior management positions in engineering and was instrumental in defining and bringing to market several generations of LogicVision’s products. From 1991 to 1995, Stephen held various engineering lead and management positions within IBM’s mainframe test group. He received his Ph.D. in Electrical Engineering from McGill University in Montreal, Canada.
Rich has over 20 years in electronics manufacturing and test. His early career included roles as a SRAM product engineer and microprocessor test and product engineer. Rich has worked with ARM for over 10 years developing and evaluating DFT methodologies while supporting DFT for hard core development and testchips.
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