The Defect-Free & High Yield DFT Solution for ARM IP

Overview

Tessent Support of ARM Cores and Memories

Mentor Graphics and ARM are partnering to provide customers with tools to deliver the most advanced, defect free and highest yielding IC products to market in a timely manner. The two companies continue to work to ensure Mentor’s Tessent family of silicon test products are optimized to provide comprehensive and cost-effective test coverage of ARM processors and memory IP.

What You Will Learn

This seminar will describe the specific test solutions developed to cover both the memory and logic test requirements of ARM-based designs. Special emphasis will be placed on recent enhancements to these solutions including improvements to the automated support of the ARM standardized MBIST (aka Shared Bus) interface. This interface enables test access to memories through the functional path, resulting in higher quality test and reduced impact on performance. The interface however requires that all of the memories attached to that interface be tested sequentially. For large memories such as L2 caches this may cause excessive test time. A new method developed by ARM to add multiple interfaces internal to the core to add flexibility to the current solution will be presented.