Mentor Graphics Design-for-Test and Verigy - Logic Diagnosis and Yield Learning

Overview

Hear from Janusz Rajski, Ph.D., Mentor Graphics on how industry experts are closing the gap between test, diagnosis and yield learning. This presentation was presented at the Mentor Graphics / Verigy seminars.

The presentation focuses on emerging solutions that use logic diagnosis to turn production test results into vehicles for yield learning. High-volume diagnosis is combined with the emerging field of design for manufacturing to enable layout aware analysis. This new approach offers advantages but it also presents many challenges including efficient collection of massive amounts of fail log data in production environment; fast and accurate diagnosis of compressed data; links to process and lithography simulation; statistical post-processing of the results; and calculation of feature failure rates.

Analysis of test data from manufacturing test is a true gold mine of information that can be used to calibrate DFM rules that are largely qualitative and compute yield sensitivity functions. By closing the loop between DFM techniques and the actual defect behavior there is the potential to not only improve yield but also provide validation and calibration of DFM rules.