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Low Pin Count Test with Embedded Compression



This event will describe several methodologies that enable designers to reduce the number of pins and top level routing required for the application of high quality test.

The focus will be on manufacturing test which requires high quality deterministic test patterns that can effectively identify manufacturing defects in silicon. Learn how to reduce test data volume and test application times while also doing so with fewer test pins. An industrial design example using just 3 pins will be presented.

Some of the common motivations for LPCT are top-level chip routing congestion, wafer test, multi-site testing, tester and design pin limitations. We’ll explain how boundary scan circuitry can be used to provide solutions to quality test while keeping the pin count to a minimum.

What You Will Learn

  • High test compression with as few as 1 or 2 test channels
  • Minimizing congestion in top level routing by using 1 or 2 test channels to access internal blocks
  • A sample of real world LPCT implementations
  • Ways to use boundary scan to achieve LPCT


About the Presenter

Presenter Image Bruce Swanson

Bruce Swanson is a Technical Marketing Engineer in the Silicon Test Solutions division at Mentor Graphics. He received an MS in applied information management from the University of Oregon and a BS in computer engineering from North Dakota State University. Bruce has over 20 years of experience in EDA and computer hardware design.

Who Should View

  • Design Engineers
  • Design for Test Engineers
  • Engineering Managers
  • Anyone involved with the financial impact of reducing test time and test cost

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