Sign In
Forgot Password?
Sign In | | Create Account

Design-for-Test Techniques for Mass Production Test

Details

Overview

Industry demands for multi-site test and specialized IO are driving the test interface to use as few pins as possible. Advanced approaches to reduced pin count testing (RPCT) combined with Xpress technology enable high quality test patterns to be applied with both a short test time and minimal test pins.

Related Resources

Multimedia

Process Technology Disruptions and the Evolution of Diagnosis Driven Yield Analysis

Recent technology nodes have each brought about new process challenges that introduced manufacturing defects which required new yield learning methods. This presentation takes a look back at the recent...…View Technology Overview

Mentor Test Announcements at 2013 ITC

Steve Pateras talks to EDA Café about what's new and hot in test from Mentor.…View Technology Overview

Tessent Product Suite Overview

Built on the foundation of the best-in-class test tools for each test discipline, Tessent® brings these solutions together in a powerful test platform that ensures total chip coverage.…View Technology Overview

Other Related Resources

Plug-and-Play Test Strategy for 3D ICs

White Paper: As the industry transitions to 3D ICs, new test strategies are being developed to meet to two 3D IC test goals: improving the pre-packaged test quality and establishing new tests between the stacked die....…View White Paper

Tessent Cell-Aware Test

White Paper: Tessent Cell-Aware ATPG is a transistor-level ATPG-based test methodology that achieves significant quality and efficiency improvements by directly targeting specific shorts; opens and transistor defects...…View White Paper

Improve Logic Test with a Hybrid ATPG/BIST Solution

White Paper: Two test strategies are used to test virtually all IC logic—automatic test pattern generation (ATPG) with test pattern compression, and logic built-in self-test (BIST). For many years, there was a...…View White Paper

 
Online Chat