New Frontiers in Scan Diagnosis
On-demand Web Seminar
Scan diagnosis is an established software-based technique for defect localization in digital semiconductor devices. In this webinar, you will learn about the most recent advances in diagnosis technology and how the role of diagnosis is expanding from just ‘where to look in PFA’ to ‘a test bed for checking hypotheses that explain what I found in PFA’. We will explore new technologies that dramatically reduce the noise in the diagnosis data, identify yield limiting design features, and address cell internal defects. The webinar includes results from industrial case studies.
What You Will Learn
In this webinar you will learn about ways that allow failure analysis to regain its effectiveness and position as a key contributor to yield improvement in digital semiconductor devices, as well as significantly improve the analysis of field returns. Topics to be covered include:
- Learn how the combination of layout-aware diagnosis and design profiling can be leveraged to find and eliminate design dependent defects.
- Understand how statistical enhancement techniques such as root cause deconvolution (RCD) eliminates noise from diagnosis data and determines the underlying root causes represented in a population of failing devices from test data alone.
- Explore cell-aware diagnosis technology that can be used to find defects inside standard cells and combat the new challenges associated with FinFET technology
About the Presenter
Geir Eide is the product marketing manager for the Silicon Learning Products in the Silicon Test Solutions group at Mentor Graphics. His current focus is on diagnosis and yield analysis. He has previously held positions related to design-for-test, semiconductor test, and silicon debug, in the design automation and semiconductor test industry. He earned BS and MS degrees in Electrical and Computer Engineering from the University of California at Santa Barbara, and has an engineering degree from Kongsberg College of Engineering, Norway.
Who Should View
- Failure analysis lab managers and engineers who use or are interested in using scan diagnosis results as part of the defect localization process
- Foundry engineering managers responsible for the collaborative effort with foundries to improve process yields
- Engineering managers and product engineers responsible for the yield of individual products
- Test and DFT engineers who enable and perform diagnosis
Process Technology Disruptions and the Evolution of Diagnosis Driven Yield Analysis
Recent technology nodes have each brought about new process challenges that introduced manufacturing defects which required new yield learning methods. This presentation takes a look back at the recent...…
ISTFA 2013 Tools of the Trade: Mentor Graphics
This video features information on Mentor Graphics' Tessent Diagnosis software, as demonstrated at ISFTA 2013's "Tools of the Trade" tour.…
Other Related Resources
Improve Failure Analysis Success Rate with Layout-Aware Diagnosis
White Paper: In this whitepaper, we explore how a layout- aware diagnosis is a powerful tool for both failure analysis engineers, who find the root cause of a particular failing die, and for yield engineers, who need...…
Root Cause Deconvolution - The Next Step in Diagnosis Resolution Improvement
White Paper: Scan logic diagnosis turns failing test cycles into valuable data and is an established method for digital semiconductor defect localization. The advent of layout-aware scan diagnosis represented a dramatic...…