3D IC Test
3D-IC technology has been getting a lot of attention in the press and at technical conferences. Whether the 3D-IC is built on Silicon Interposers or stacked die with Through Silicon Vias, Mentor Graphics is uniquely positioned to support our customers with both the Calibre and Tessent product lines.
Steve Pateras talks to EDA Café about what's new and hot in test from Mentor.…View Technology Overview
Built on the foundation of the best-in-class test tools for each test discipline, Tessent® brings these solutions together in a powerful test platform that ensures total chip coverage.…View Technology Overview
Other Related Resources
White Paper: Two test strategies are used to test virtually all IC logic—automatic test pattern generation (ATPG) with test pattern compression, and logic built-in self-test (BIST). For many years, there was a...…View White Paper
White Paper: The creation of test patterns for mixed signal IP has been, to a large extent, a manual effort. To improve the process used to test, access, and control embedded IP, the new IEEE P1687 standard 1 is being...…View White Paper