3D IC Test
3D-IC technology has been getting a lot of attention in the press and at technical conferences. Whether the 3D-IC is built on Silicon Interposers or stacked die with Through Silicon Vias, Mentor Graphics is uniquely positioned to support our customers with both the Calibre and Tessent product lines.
Recent technology nodes have each brought about new process challenges that introduced manufacturing defects which required new yield learning methods. This presentation takes a look back at the recent...…View Technology Overview
Steve Pateras talks to EDA Café about what's new and hot in test from Mentor.…View Technology Overview
Other Related Resources
White Paper: As the industry transitions to 3D ICs, new test strategies are being developed to meet to two 3D IC test goals: improving the pre-packaged test quality and establishing new tests between the stacked die....…View White Paper
White Paper: Tessent Cell-Aware ATPG is a transistor-level ATPG-based test methodology that achieves significant quality and efficiency improvements by directly targeting specific shorts; opens and transistor defects...…View White Paper
White Paper: Two test strategies are used to test virtually all IC logic—automatic test pattern generation (ATPG) with test pattern compression, and logic built-in self-test (BIST). For many years, there was a...…View White Paper