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David Abercrombie at DAC 2012

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Why IC Designers Need New Double Patterning Debug Capabilities at 20nm

Jean-Marie Brunet, Director of DFM Product Marketing, discusses Mentor's history of collaboration with TSMC and highlights their work on design enabling support for 20nm.…View Technology Overview

Macro Placement in Olympus-SoC

This video shows the automatic macro placment capabilities in the Olympus-SoC place and route system. It also shows examples of the improved design metrics the Olympus-SoC macro placer achieves.…View Product Demo

Michael Buehler at DAC 2012

Interview with Mentor Graphics' Michael Buehler at DAC 2012.…View Technology Overview

Other Related Resources

Double Patterning from Design Enablement to Verification

White Paper: Litho-etch-litho-etch (LELE) is the double patterning (DP) technology of choice for 20 nm contact, via, and lower metal layers. We discuss the unique design and process characteristics of LELE DP, the challenges...…View White Paper

Self-aligned double-patterning (SADP) friendly detailed routing

White Paper: Among the possible double patterning strategies, self-aligned double patterning (SADP) has moved from Flash-only processes to more general purpose devices. The reason is that while lithoetch-litho-etc (LELE)...…View White Paper

Routing Technology for Advanced-Node IC Designs

White Paper: As the IC industry accelerates towards the adoption of 32nm and 28nm process nodes, designers face significant new challenges with digital routing. These challenges to sub-nanometer routing—including...…View White Paper

 
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