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Tessent Test Solutions: Advanced Solutions Covering Both the 2D and 3D Spaces - DAC 2012

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The growing adoption of 3D packages is driving new test needs like very low pre-packaged die escape rates, and new test access methods for stacked die in packages. Come to Mentor’s silicon test session to learn about 3D-IC testing, as well as test solutions for embedded and shared bus ARM memories, and new cell-aware testing techniques.


Design Areas Silicon Test and Yield Analysis
Design Tasks Logic Test, Memory Test, Mixed-Signal Test, Silicon Learning
Online Chat