Power-Aware Silicon Test: Understanding Testing and Power-Sensitive Designs
On-demand Web Seminar
This session will discuss the trends, drivers and solutions for power-aware test that have emerged recently. We will discuss the technologies where power-aware test is required and how designers are looking to address these issues. We will also discuss the impact power-aware test has on test planning and on test generation.
Over the last few years, managing power during test has become more important, and more challenging. Designers tend to focus on 2 areas when it comes to silicon test and power; low-power ATPG and power-aware test.
During silicon test, test-vector volume and execution time are tracked to minimize the cost of test. As a result, the goal for automatic test pattern generation (ATPG) is to achieve the maximum coverage with the minimum number of test patterns. This produces a conflict with the goal of managing power and testing power domains, because, to get the highest quality test results, the IC under test can be operated beyond its normal functional modes. This can result in false failures and in some cases will affect product reliability or cause permanent damage to the IC. Controlling the switching level during automatic test program generation (ATPG) to stay within the power budget is important for low-power ATPG.
Devices that are designed for use in low-power applications include many structures to manage power. In addition to functional logic to control power, these designs also use retention cells, to remember the last-state of the logic prior to power-down, isolation cells, and level shifters. Power-aware silicon test solutions must identify, manage and accurately test these features in order to guarantee high-quality devices.
What You Will Learn
- Designs approaches which are in the forefront of low power test
- Compelling reasons for addressing low power test issues
- The test solutions available for low power test
About the Presenter
Kan Thapar is the European Product Specialist for the Mentor Graphics Test tools. He works with leading global electronic companies in Europe and India at the technical management level on addressing their crucial test needs for high volume products. This involves high level management meetings on understanding their needs and promoting Mentor Graphics test tools. He is participating in various collaborative initiatives to introduce advanced test methodologies to these Mentor customers. He has organised technology seminars on Test for the European customers, as well as, expert panels for the DATE conferences. He has been co-author on papers in technical test journals. He has been with Mentor Graphics for 14 years and has previously supported the Design Entry, Simulation, Emulation, Formal Verification, ASIC Synthesis and Test products in a technical sales capacity.
Before joining Mentor Graphics, he was at GEC Hirst Research Centre where he managed a project team to design ASICs for Telecommunications products. He has extensive and in-depth experience as a VLSI and ASIC designer for multi-media, DSP and military products from conception to tapeout. He published papers internally and for EU electronic collaborative projects such as ESPRIT and the UK Alvey projects.
He holds a B.Sc. in Mathematics and a M.Sc. in Digital Systems. He has completed an Open University course on Effective Management.
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