Yield Improvement by Scan Chain Defects Diagnosis
On-demand Web Seminar
Defects in test structures such as scan chains often contribute to as much as 50% of semiconductor manufacturing test failures. Identifying and localizing scan chain failures can be a tedious and costly process often performed using dedicated, expensive equipment. Today’s complex designs and advanced manufacturing processes make defect diagnosis the most time-consuming step.
Learn methodologies for yield improvement of semiconductor devices through scan chain diagnosis. Scan chain diagnosis, a software-based technique, can effectively identify scan chain defects. This chain diagnosis flow has been successfully applied in industrial practice to achieve a high physical failure analysis success rate and improved yield.
- Defects and corresponding fault models that can cause scan chain shift to fail
- Techniques for diagnosing scan chain failures to identify defective locations
- Chain diagnosis application flow for single-die diagnosis and yield analysis
- Case studies to show how to take advantage of scan chain diagnosis and results to improve yield
About the Presenter
Yu Huang, Ph.D.
Yu Huang, Ph.D. is currently senior member of staff in the Advanced Research Group within the Silicon Test Solutions Division at Mentor Graphics. He has published over 80 technical papers for leading journals, international conferences, and workshops. He has six US and international patents approved and eight patents pending. He was invited as program committee member or panelist in several conferences including ITC, VTS, ATS, ETS, ASPDAC, SEMICON, VALID, NATW, and WRTLT. He received his Ph.D. in electrical and computer engineering from the University of Iowa.
Who Should View
- Engineers and managers responsible for product design, testing, quality, and yield
- Engineers and managers responsible for digital semiconductor product and technology advancement
- Failure analysis lab managers and process engineers
- Engineers involved in manufacturing production and process development
- Anyone involved with the financial impact of low yield and low product quality
ISTFA 2013 Tools of the Trade: Mentor Graphics
This video features information on Mentor Graphics' Tessent Diagnosis software, as demonstrated at ISFTA 2013's "Tools of the Trade" tour.
Accelerating Yield and Failure Analysis with Diagnosis
In this webinar you will learn about ways that allow failure analysis to regain its effectiveness and position as a key contributor to yield improvement in digital semiconductor devices, as well as significantly...
Identifying Systematic Yield Limiters Using Scan Test Diagnosis
At ISTFA 2012 , Mentor Graphics' Geir Eide, talks about how to identify systematic yield limiters using scan test diagnosis results. The International Symposium on Testing and Failure Analysis (ISTFA),...