Scan Failure Diagnosis - YieldAssist / Calibre Demo
On-demand Web Seminar
Details
Overview
The YieldAssist/Calibre demo first highlights the use of physical layout data in Calibre to identify high-risk net pairs which are susceptible to bridging defects. Next, TestKompress is used to generate compressed patterns targeting each of the selected net pairs for the bridging fault model. Tester failure files are then analyzed by YieldAssist to identify, classify, and prioritize defect suspects. Finally, the viewing of defect suspects in the logical (gate) and physical (layout) environments is demonstrated.Related Resources
Multimedia
Calibre DFM: DFM is Mandatory and Enables a Competitive Advantage
Calibre DFM is a complete offering for stand-alone signoff solutions and for solutions integrated to all design flows, such as custom analog and P&R. You will learn how Calibre DFM signoff can be used...…View On-demand Web Seminar
Foundry Solutions Video Blog: TSMC OIP Conference
At TSMC's Open Innovation Platform (OIP) Ecosystem Forum, Mentor made technical presentations on four different topics, two of them co-presented with TSMC and LSI Corporation. Those presentations are described...…View Technology Overview
Michael Buehler at DAC 2012
Interview with Mentor Graphics' Michael Buehler at DAC 2012.…View Technology Overview
Other Related Resources
Thickness-aware LFD for the hotspot detection induced by topology
White Paper: A methodology of advanced process window simulations with awareness of chip topology is presented. This method identifies the expected focal range encountered due to different topology in different areas...…View White Paper
Calibre Fundamentals: DFM Case Studies
Training Course: Calibre Fundamentals: DFM Case Studies introduces you to the state-of-the-art tools and processes required for success when designing deep sub-micron integrated circuits.…View Training course
The Roadmap to LFD Value: Quantifying a Return on Investment in Calibre LFD
White Paper: By the time a serious lithographic problem is identified at the fab, it is too late in the design process to make a simple layout change, resulting in a significant delay of the tapeout, and consequently...…View White Paper