Mentor Design-for-Test and Verigy - Zero Overhead Diagnosis - Enabling fastest yield ramp for 65nm and beyond
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Hear from Ajay Koche, Ph.D., Verigy, Semiconductor Test Solutions, on how state-of-the-art ATE can deliver cost efficient data collection in volume manufacturing today when taking full advantage of a true test processor per pin architecture.
Duration: 52:32
Products: Tessent Diagnosis, Tessent FastScan, Tessent TestKompress
Details
Overview
Hear from Ajay Koche, Ph.D., Verigy, Semiconductor Test Solutions, on how state-of-the-art ATE can deliver cost efficient data collection in volume manufacturing today when taking full advantage of a true test processor per pin architecture. Dr Koche presents how efficient data collection of relevant failure information for high-volume diagnosis also supports the need for lowering cost of test.
The presentation also shows how such an ATE architecture can eventually deliver "zero overhead" data collection for taking full advantage of parallel multi-site testing. Integration with semiconductor manufacturing environments is shown using practical examples and results.
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