News & Press

Mar 8, 2012

Nov 11, 2011

Mentor Graphics Announces Completion of 20 nm Test Chip Tapeout with STMicroelectronics Using Olympus-SoC Place and Route System (Nov 4, 2011)
ARM and Mentor Graphics Define Comprehensive Test Methodology for ARM-based Designs (Sep 19, 2011)
Mentor Graphics Adds User Defined Fault Models and Cell-Aware ATPG to Improve IC Test Quality (Sep 19, 2011)
Mentor Graphics and GLOBALFOUNDRIES Improve Yield Analysis with Combination of Tessent and Calibre Capabilities (Aug 29, 2011)
Mentor Graphics Mines Design and Test Data to Improve IC Yield and Failure Analysis (Jun 3, 2011)
Mentor Graphics Provides Calibre Verification and Tessent Test Solutions for 3D-IC in TSMC Reference Flow 12 (Jun 2, 2011)
Mentor Graphics Addresses 28nm and 3D-IC Requirements in TSMC Reference Flow 12 (Jun 2, 2011)
Mentor Graphics Outlines Strategy for 3D-IC Design, Verification and Testing (Mar 29, 2011)

Tips for testing processor cores (Apr 6, 2012)
Dual Approach to Chip Test (Mar 23, 2012)
Cell-aware ATPG test methods improve test quality (Mar 6, 2012)
Determining the best test patterns for production test - You need to collect data before you can decide on the best test strategy. (Mar 6, 2012)
3D chip design explored by Mentor Graphics (Feb 20, 2012)
Memory BIST for shared-bus applications (Feb 1, 2012)
Understanding Cell-Aware ATPG And User-Defined Fault Models (Feb 1, 2012)
Semiconductor yield improvement with scan diagnosis (Nov 16, 2011)
Diagnosis-Driven Yield Analysis Improves Mature Yield (Nov 7, 2011)
Direct diagnosis for compressed ATPG patterns: A successful industrial experiment with layout-aware diagnosis (Oct 19, 2011)
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