News & Press

Nov 6, 2012

Oct 23, 2012

TSMC Presents Two Partner of the Year Awards to Mentor Graphics for 20nm and 3D IC Design Flows (Oct 16, 2012)
Mentor Graphics Provides Design, Verification and Test Solutions for TSMC’s 20nm Design Infrastructure (Oct 15, 2012)
Mentor Graphics Provides Design, Verification, Thermal and Test Solutions for TSMC’s CoWoS Reference Flow (Oct 15, 2012)
Calibre Flow Developed with Mentor Graphics Consulting Boosts GLOBALFOUNDRIES Silicon Yield (Mar 8, 2012)
Mentor Graphics Receives TSMC’s Partner of the Year Award for 3D-IC Design Enablement (Nov 11, 2011)
Mentor Graphics Announces Completion of 20 nm Test Chip Tapeout with STMicroelectronics Using Olympus-SoC Place and Route System (Nov 4, 2011)
ARM and Mentor Graphics Define Comprehensive Test Methodology for ARM-based Designs (Sep 19, 2011)
Mentor Graphics Adds User Defined Fault Models and Cell-Aware ATPG to Improve IC Test Quality (Sep 19, 2011)

Boost DFT efficiency for large SoCs (Apr 23, 2013)
Optimizing autonomous IC test without sacrificing precision (Feb 26, 2013)
Use a smarter DFT tool environment for better design customization (Feb 5, 2013)
Mentor Snags Two Awards at DesignCon (Jan 29, 2013)
What's the difference between Scan ATPG and IJTAG Pattern Retargeting (Jan 22, 2013)
What's The Difference Between Scan ATPG And IJTAG Pattern Retargeting? (Jan 22, 2013)
Dreaming of plug-and-play IP (Dec 17, 2012)
Plug-n-play access and control of embedded IP (Dec 12, 2012)
IJTAG: delivering an industry platform for IP test and integration (Nov 16, 2012)
For Better IC Production Test: Cell-Aware Fault Models," by Friedrich Hapke, Mentor Graphics and Stefan Eichenberger, NXP (Sep 25, 2012)
Articles Archives