Silicon Test and Yield Analysis News Archive

November 2011

Mentor Graphics Receives TSMC’s Partner of the Year Award for 3D-IC Design Enablement Nov 11, 2011

Mentor Graphics Announces Completion of 20 nm Test Chip Tapeout with STMicroelectronics Using Olympus-SoC Place and Route System Nov 4, 2011

September 2011

ARM and Mentor Graphics Define Comprehensive Test Methodology for ARM-based Designs Sep 19, 2011

Mentor Graphics Adds User Defined Fault Models and Cell-Aware ATPG to Improve IC Test Quality Sep 19, 2011

August 2011

Mentor Graphics and GLOBALFOUNDRIES Improve Yield Analysis with Combination of Tessent and Calibre Capabilities Aug 29, 2011

June 2011

Mentor Graphics Mines Design and Test Data to Improve IC Yield and Failure Analysis Jun 3, 2011

Mentor Graphics Provides Calibre Verification and Tessent Test Solutions for 3D-IC in TSMC Reference Flow 12 Jun 2, 2011

Mentor Graphics Addresses 28nm and 3D-IC Requirements in TSMC Reference Flow 12 Jun 2, 2011

March 2011

Mentor Graphics Outlines Strategy for 3D-IC Design, Verification and Testing Mar 29, 2011

Mentor Graphics Tessent YieldInsight Demonstrates Faster IC Failure and Yield Analysis at Fujitsu Mar 18, 2011

January 2011

STARC Advances Test of Low Power ICs Using Mentor Graphics Tessent TestKompress Jan 24, 2011