Mentor Graphics and GLOBALFOUNDRIES Improve Yield Analysis with Combination of Tessent and Calibre Capabilities
WILSONVILLE, Ore., August 29, 2011 - Mentor Graphics Corporation (NASDAQ: MENT) today announced an innovative approach to IC yield analysis that combines the layout-aware production test failure diagnosis capabilities of the Tessent® Diagnosis and Tessent YieldInsight® products with the design for manufacturing (DFM) analysis facilities of the Calibre® YieldAnalyzer tool. The new methodology enables customers to identify and understand systematic yield loss, and to determine if the systematic yield loss is correlated to DFM violations.
“Diagnosis-driven yield analysis is an established yield-learning methodology at GLOBALFOUNDRIES for internal technology development, as well as for accelerating the yield ramp for our customer products,” said Thomas Herrmann, MTS product engineer, GLOBALFOUNDRIES. “The addition of DFM-aware yield analysis helps us and our customers to separate design-and process-related yield limiters, and reduces the time to find the root causes of yield loss. We can also use the technology to optimize DFM rules to address specific customer needs and priorities, which leads to reduced manufacturing variability for re-spins and future designs.”
In the DFM-aware yield analysis flow, test data from digital semiconductor devices that have failed manufacturing test is used to perform layout-aware failure diagnosis with the Tessent Diagnosis product, which provides information such as defect classifications and suspected defect locations. The Calibre YieldAnalyzer product leverages GLOBALFOUNDRIES’ Manufacturing Analysis and Scoring (MAS) deck to identify features of the layout that have higher sensitivities to manufacturing variability. The Tessent YieldInsight product analyzes this information to identify and understand systematic yield loss, and determine if this yield loss is associated with known DFM-sensitive layout structures.
“Mentor continues to drive towards meaningful interactions between the design and manufacturing test flows,” said Greg Aldrich, marketing director for the Silicon Test Solutions group at Mentor Graphics. “This is much more than allowing tools to exchange data—it’s incorporating powerful data mining and statistical analysis capabilities that leverage the knowledge and experience of experts from both the design and manufacturing areas.”
About Mentor Graphics
Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues over the last 12 months of about $915 million. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.
(Mentor Graphics, Calibre, Tessent and YieldInsight are registered trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.)
For more information, please contact:
Gene Forte
Mentor Graphics
503.685.1193
gene_forte@mentor.com
Sonia Harrison
Mentor Graphics
503.685.1165
sonia_harrison@mentor.com
Silicon Test and Yield Analysis Press Releases
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- Mentor Graphics and GLOBALFOUNDRIES Improve Yield Analysis with Combination of Tessent and Calibre Capabilities (Aug 29, 2011)
- Mentor Graphics Mines Design and Test Data to Improve IC Yield and Failure Analysis (Jun 3, 2011)
- Mentor Graphics Provides Calibre Verification and Tessent Test Solutions for 3D-IC in TSMC Reference Flow 12 (Jun 2, 2011)
- Mentor Graphics Addresses 28nm and 3D-IC Requirements in TSMC Reference Flow 12 (Jun 2, 2011)
- Mentor Graphics Outlines Strategy for 3D-IC Design, Verification and Testing (Mar 29, 2011)