WILSONVILLE, Ore., October 23, 2012—Mentor Graphics Corp. (NASDAQ: MENT) today announced that KALRAY S.A. has completed its new 160 million gate, three billion transistor Multi-Purpose Processor Array IC using a Mentor Graphics® functional verification, physical design and verification, and design-for-test flow incorporating the Questa®, Olympus-SoC™, Calibre® and Tessent® product suites.
“Undertaking a project like this at the leading edge process node demanded best-in-class tools for each step of the process,” said Joël Monnier, CEO at KALRAY. “Our design methodology is based on a multi-level hierarchical approach in order to optimize performance, to take advantage of a modular and repetitive design and to overcome implementation complexity. The fact that Mentor’s platforms work together seamlessly is a definite productivity enhancer, but just as critical, each tool needs to have the features, speed, accuracy and capacity to handle designs at this scale. Mentor also stands apart as the most trusted EDA partner, thanks to the quality of its products and service, to ensure designs are ‘first time right,’ including being ready for high-volume manufacturing.”
The KALRAY MPPA®-256 manycore processor is a 256-core SoC with 47MB memory. It is organized as 16 clusters of 16 cores and is implemented using 28nm manufacturing process technology. The cores work in parallel and communicate together via a high-speed low-latency Network-on-Chip, just as large clusters of computers do in a datacenter. Multiple MPPA® chips can be interconnected at the PCB level through Interlaken interfaces to increase the processor array size and performance capability. MPPA manycore processors target the embedded computing market in such sectors as image and signal processing, scientific computing, data security, industrial, aeronautics and transportation.
KALRAY employed an OVM-based functional verification methodology using the Mentor® Questa product, which provides AXI protocol support in the Questa Verification IP Library. For physical design (layout), they chose the Olympus-SoC place-and-route system for its ability to handle large capacity hierarchical designs with multi-threaded routing and timing analysis, multi-corner multi-mode based multi-voltage flow, and built-in Calibre signoff inside the Olympus-SoC system. The Calibre platform, including Calibre nmDRC, Calibre nmLVS and DFM tools, was used for its large capacity and high performance. KALRAY was able to run DRC in multi-threaded mode with up to 160 CPUs to reduce turnaround time. (All KALRAY target foundries recommend the Calibre suite for verification and DFM.) KALRAY chose the Tessent silicon test platform for memory built-in self-test (BIST) implementation and for high-compression automatic test pattern generation (ATPG) of both stuck-at and high-speed transition fault tests.
“While complexity and design sizes keep increasing at advanced technology nodes, time-to-market windows stay the same, or get even smaller,” said Pravin Madhani, general manager for the Place and Route division at Mentor Graphics. “Mentor’s design implementation, test, and verification platforms ensure scalability, reliability and predictable time-to-design closure, making a profound difference in the ability to get complex SoCs to market on time.”
(Mentor Graphics, Mentor, Questa, Calibre and Tessent are registered trademarks and Olympus-SoC is a trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.)