Mentor Graphics TestKompress leading ATPG tool to use SDQM to target delay defects

WILSONVILLE, Ore., May 9, 2007 – Mentor Graphics Corporation (Nasdaq: MENT) today announced with the Semiconductor Technology Academic Research Center (STARC) that Mentor’s ATPG tool, TestKompress®, will be used to target small delay defects using the Statistical Delay Quality Model (SDQM). STARC, a research consortium co-founded by eleven major Japanese semiconductor companies, developed the SDQM to enable scan-based automatic test pattern generation (ATPG) to detect small delay defects that could become more prevalent at technology nodes of 90nm and below.

The collaborative efforts between STARC and Mentor Graphics now make it possible for design-for-test (DFT) engineers to apply the SDQM while using an ATPG tool that leads the industry in high quality test and test pattern compression. The combination of these features means users can improve the effectiveness of their test while maintaining low production test costs.

“In a continuing effort to supply proven technology to our member companies, STARC strives to achieve alignment between EDA tool providers and the technology we develop” said Mr. Yoshio Okamura, Executive Director and Division Manager of Development Department-2 at STARC. “We will continue this close working relationship to make Mentor DFT tools a primary conduit for future DFT technology developed by STARC.”

TestKompress uses SDQM to target small delay defects by sensitizing paths with minimum delay “slack,” which typically represent the most critical paths in a design. To determine the most effective SDQM paths, the TestKompress tool uses the timing information imported from a design’s standard delay format (SDF) file. To report the effectiveness of these test pattern sets, a statistical metric is reported that compares the sensitized paths to the longest possible paths.

“We are delighted that STARC has chosen Mentor Graphics as its EDA partner for DFT,” said Robert Hum, vice president and general manager of the Design Verification and Test Division of Mentor Graphics. “We think that the combination of the SDQM technology coupled with the high levels of pattern compression available from TestKompress will help users achieve their test quality goals.”

The Semiconductor Technology Academic Research Center, STARC, is a research consortium co-founded by major Japanese semiconductor companies in December 1995. STARC's mission is to contribute to the growth of the Japanese semiconductor industry by developing leading-edge SoC design technologies.

About Mentor Graphics
Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $800 million and employs approximately 4,250 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.

(Mentor Graphics and TestKompress are registered trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.)

For more information, please contact:
Gene Forte
Mentor Graphics
503.685.1193
gene_forte@mentor.com

Sonia Harrison
Mentor Graphics
503.685.1165
sonia_harrison@mentor.com