Tessent Product Line
Tessent® BoundaryScan automates adding IEEE 1149.1 standard boundary scan support to ICs of any size or complexity. The boundary scan logic can be accessed throughout the life of the IC, including manufacturing test at all package levels, silicon debug, and system verification.
Tessent® Diagnosis performs accurate and high-resolution test failure diagnosis to determine a defect’s most probable failure mechanism, logic location, and physical location. The tool uses failure data from manufacturing test, scan test patterns, and design information. With this data, Tessent Diagnosis identifies the location and classification of the defect causing the failure.
Tessent® FastScan™ is an ATPG solution with a wide range of fault models, comprehensive design rules checks, extensive clocking support, and innovative algorithms for performance-oriented pattern compaction, making it the most versatile ATPG tool available.
Tessent ® IJTAG provides automation to support the emerging IEEE P1687 standard for plug-and-play IP integration. Tessent IJTAG simplifies the process of connecting any number of IEEE P1687 compliant IP blocks into an integrated, hierarchical network and to communicate commands to the blocks from a single access point.
Tessent® LogicBIST is the industry’s leading built-in self-test solution for testing the digital logic components of integrated circuits. It includes unique features targeted at nanometer SoC designs that reduce test costs and shorten time-to-market while maximizing test quality.
Tessent MemoryBIST provides a complete solution for at-speed testing, diagnosis, and repair of embedded memories. The solution’s architecture is hierarchical, allowing BIST and self-repair capabilities to be added to individual cores as well as at the top level.
Tessent PLLTest provides complete, parametric, embedded test for PLLs, DLLs, and clock signals.
Tessent Scan inserts scan test structure into a netlist. The output is design that is completely ready for scan testing and pattern compression.
Tessent SerdesTest provides complete, parametric, embedded test for multi-Gb/s SerDes.
Tessent® SiliconInsight® provides an automated interactive environment for test bring-up, debug, and silicon characterization of devices containing Tessent BIST capabilities. It can greatly increase productivity for chip designers and test engineers during silicon validation and debug, speeding time-to-market. Tessent SiliconInsight reduces test and silicon bring-up time with interactive debug and characterization for benchtop environments.
Tessent® SoCScan complements the Mentor Graphics ATPG solutions, Tessent TestKompress and Tessent FastScan, by providing an environment to insert a hierarchical scan and clock control infrastructure for at-speed testing and effective test reuse.
Tessent® TestKompress® is the industry-leading ATPG tool that provides the highest quality scan test with the absolute lowest test cost. TestKompress has an industry-proven ATPG engine that applies effective fault models to the entire logic design. Manufacturing test costs are held in check by an award-winning test pattern compression technique called Embedded Deterministic Test (EDT).
Tessent® YieldInsight statistically analyzes diagnosis data to identify and separate systematic yield limiters before failure analysis. This eliminates the need for costly physical localization and reduces the time to determining root cause of yield loss from weeks to days. Selection of die for failure analysis is facilitated by automatically identifying die that clearly exhibit the identified systematic issues.