Tessent BoundaryScan
Tessent® BoundaryScan automates adding IEEE 1149.1 standard boundary scan support to ICs of any size or complexity, reducing IC engineering development effort and improving time-to-market.
The boundary scan logic can be accessed throughout the life of the IC, including manufacturing test at all package levels, silicon debug, and system verification. The result is both I/O cell defects and inter-IC board interconnect problems are detected before shipment, reducing field support costs and increasing customer satisfaction.
Features and Benefits
- Extensive fault model support, including stuck-at, IDDQ, transition, path delay, and bridge.
- On-chip PLL support for accurate at-speed test.
- Ensures the highest performance ATPG for full and structured partial scan designs.
- Reduces run time with no effect on coverage or pattern count using distributed ATPG.
- Reduces test validation time with automatic simulation mismatch debugging.
- Minimizes the effect of Xs and provide higher coverage with false and multicycle support.
- Identifies testability problems early using comprehensive design rule checking.
Tessent BoundaryScan AC Option
- IEEE 1149.6 Boundary Scan
- Generates and integrates RTL code for 1149.6-compliant TAP controller and boundary scan cells.
Product Demo
This product presentation describes the advantages of using Tessent BoundaryScan for managing both internal and external tests. This tool is compliant with IEEE standards 1149.1 and 1149.6 to provide extensive...
Datasheet
Tessent Training
We have training courses available for Tessent products in our training centers around the world, online, or at your site.
Contact Mentor Graphics
- Tessent BoundaryScan Info Request or call toll free: 1-800-547-3000