Tessent® BoundaryScan automates adding IEEE 1149.1 standard boundary scan support to ICs of any size or complexity, reducing IC engineering development effort and improving time-to-market.
The boundary scan logic can be accessed throughout the life of the IC, including manufacturing test at all package levels, silicon debug, and system verification. The result is both I/O cell defects and inter-IC board interconnect problems are detected before shipment, reducing field support costs and increasing customer satisfaction.
Features and Benefits
- Ready-to-use library of boundary scan cells, testbenches to automate verification in simulation, short test times, and minimal tester hardware requirements reduce IC development costs.
- Quick boundary scan integration, automated rule checking with interactive debug, and quick integration into board test programs shorten time-to-market.
- Detecting IC I/O cell defects and enabling effective testing of inter-IC connections reduce field returns.
- Comprehensive hierarchical RTL integration and verification flow.
- Support for user-defined boundary scan cells including those embedded in sub-blocks or cores.
- Comprehensive contactless testing of I/Os.
- Support for both the IEEE 1149.1 and 1149.6 standards.
- Fully plug-and-play compatible with the complete set of the Mentor Graphics Tessent products and capabilities.
Tessent BoundaryScan AC Option
- IEEE 1149.6 Boundary Scan
- Generates and integrates RTL code for 1149.6-compliant TAP controller and boundary scan cells.
We have training courses available for Tessent products in our training centers around the world, online, or at your site. Tessent training courses