Tessent® FastScan™ simplifies the process of generating high-coverage compact test sets. Its ability to be applied to most any type of design makes it the most versatile ATPG solution available. Comprehensive at-speed test is critical to ensure high-quality testing. Tessent FastScan’s at-speed tests include transition, multiple detect transition, timing-aware, and critical path.
Benefits and Features
- Extensive fault model support, including stuck-at, IDDQ, transition, path delay, and bridge.
- On-chip PLL support for accurate at-speed test.
- Ensures the highest performance ATPG for full and structured partial scan designs.
- Reduces run time with no effect on coverage or pattern count using distributed ATPG.
- Minimizes the effect of Xs and provide higher coverage with false and multicycle support.
Tessent FastScan MacroTest Option
- Automates testing small embedded memories and cores with scan.
- Identifies testability problems early using comprehensive design rule checking.
- Reduces test validation time with automatic simulation mismatch debugging.
Tessent FastScan can be used with Tessent SoCScan to take advantage of the Mentor Graphics automated hierarchical test integration and test generation flow. Tessent SoCScan makes use of shared isolation and capture-by-domain technologies to deliver independent core-level ATPG and chip-level pattern reuse. Tessent SoCScan