To manage the complex requirements of testing a heterogeneous set of embedded IP, the industry developed IEEE P1687 (IJTAG). It standardizes a language for describing the IP interface and how IPs are connected to each other. It also introduces a language that defines how patterns that operate or test the IP are to be described. IEEE P1687 draws a clear line between what must be covered by the standard and what is better left to the ingenuity of the tool developers.
Tessent ® IJTAG is the first product of its kind, bringing IEEE P1687 to life. Tessent IJTAG provides automation and features far beyond the basic implementation of the languages of IEEE P1687. It simplifies the process of connecting any number of IEEE P1687 compliant IP blocks into an integrated, hierarchical network and to communicate commands to the blocks from a single top level access point. It provides a flow in which the user does not need to know the ins-and-outs of IEEE P1687, but can leave it up to Tessent IJTAG to find the best possible solution for his IEEE P1687 compliant design.
- Uniform access and usage of embedded IEEE P1687 compliant IP independent of the IP source
- Expands availability of embedded IP choices
- Reduces design schedules by accelerating integration of IEEE P1687 compliant IP
- Achieves minimum cycle count for accessing IP within a reconfigurable network
- Provides a common integration flow and access network for Tessent IP and any 3rd party IEEE P1687 compliant IP.
Tessent IJTAG provides value to all key contributors of a product development team.
Can use Tessent IJTAG to ensure compliance of their IP to the standard. They can also validate the functionality of the IP through simulation test benches, generated by Tessent IJTAG
Diagnosis and Failure Analysis Engineers
Use Tessent IJTAG to gain access to deeply embedded IPs as well as instruments for on-chip measurements, like power or temperature sensors. With Tessent IJTAG, they can quickly generate additional stimuli to any IP in the IJTAG network, without knowing the exact embedding of the IP in the design, without having the Verilog or RTL design files.
Can integrate IEEE P1687 compliant IP from various sources into their design, do not need to manually generate IJTAG network files for the IP interconnections they have already integrated into the design. Tessent IJTAG does the IJTAG network file creation for them, fully automatically, so they can concentrate on the design tasks, leaving the IJTAG job to the tool.
Use Tessent IJTAG to assemble and execute tests for all compliant IPs connected to the IJTAG network. Tessent IJTAG targets the smallest possible number of shift cycles that implement the described test. It saves the computed patterns in common test pattern formats as well as simulation test benches.