Tessent® LogicBIST is the industry’s leading built-in self-test solution for testing the digital logic components of integrated circuits. It includes unique features targeted at nanometer SoC designs that reduce test costs and shorten time-to-market while maximizing test quality.
Tessent LogicBIST is a fully hierarchical solution that provides full test portability for cores as well as full test reuse throughout the product life cycle.
- High transition fault coverage, signal integrity screening, and high coverage of unmodeled defects reduces field returns.
- Quick insertion of logic BIST structures, reduced test debug times, and fully reusable embedded test inserted cores shortens time-to-market.
- Minimal tester hardware requirements reduces test costs. A patented test timing architecture for effective at-speed test application and power control.
- Comprehensive RTL or gate-level automation flow for fast test integration. High bandwidth pseudorandom test pattern application for high N-detect (defect coverage).
- IEEE 1500–compliant distributed test access architecture and patented core shared isolation for hierarchical test integration.
- Hierarchical embedded solution means full test portability for cores.
- Provides full test reuse throughout the entire product life cycle.
- No test patterns to manage means a highly predictable hand-off to manufacturing.
Tessent LogicBIST can be used as a stand-alone test strategy or in conjunction with Tessent TestKompress®. The combination of the two solutions enables application of any combination of pseudorandom, deterministic, or compressed deterministic patterns. This provides the maximum flexibility for achieving the most effective test time versus quality optimization. Tessent TestKompress