Tessent® MemoryBIST provides a complete solution for at-speed testing, diagnosis, and repair of embedded memories. The solution’s architecture is hierarchical, allowing BIST and self-repair capabilities to be added to individual cores as well as at the top level.
Tessent MemoryBIST includes a unique comprehensive automation flow that provides design rule checking, test planning, integration, and verification all at the RTL or gate level..
Features and Benefits
- Fast self-test and self-repair IP integration, as well as reuse of embedded memory test inserted cores, shorten time-to-market.
- Design-time algorithm programming allows for quality improvement and test time optimization.
- Field algorithm programming provides full control of quality and test time trade-offs.
- Built-in row- and column-based repair analysis reduces test time for repairable memories.
- Tessent MemoryBIST Repair
- Tessent MemoryBIST Field Programmable
- On-chip eFuse-based repair supports any third-party repairable SRAMs.
- Supports any number of power domains distributed across any number of physical blocks.
Technology Overview & Product Demo
In today’s ICs, memory commonly can take up more than 50% of the available silicon area. There is a growing need to make changes to the test algorithms during manufacturing test, and repairable memories... View Video
Memory BIST and Repair - The industry-leading memory built-in self-test tool for high quality embedded test
Learn about memory built-in self test, hard and field programmable test algorithms for maximum defect coverage and how using self-repair can recover lost yield. View Video