Tessent® Scan™ inserts scan test structure into a netlist, delivering design that is completely ready for scan testing and pattern compression.
Tessent Scan generates and adds the most effective scan architecture for your design, ensuring high-quality test with automatic test pattern generation (ATPG). It performs scan flop replacement and stitching, analyzes your circuit for possible test limitations, does test-related design rule checks (DRCs), and automatically corrects errors.
Features and Benefits
- Works within any tool environment to improve test quality
- Provides intelligent scan insertion and connection at all levels of design hierarchy
- Supports Mux-DFF, Clocked-Scan, LSSD, and mixed design styles
- Performs extensive design rules checking to identify testability trouble spots early in the design cycle
- Automatically corrects many common testability problems
- Supports layout-based scan ordering for optimal chain layout.
- Inserts IEEE 1500-compliant test structures to enable block-based testing strategies for SoC designs.
We have training courses available for Tessent products in our training centers around the world, online, or at your site. Tessent training courses
Tessent Scan facilitates ATPG with TestKompress and FastScan by generating the required input dofile for these tools.