Tessent® SerdesTest provides complete, parametric, embedded test for multi-Gb/s SerDes. It measures waveshape, many types of jitter, and various jitter tolerance parameters, all in less than 200 ms, including test set-up and on-chip comparison to test limits via an IEEE 1149.1 TAP interface.
Tessent SerdesTest uses unlimited time-resolution analysis (ULTRA) patented technology connected to only the SerDes parallel ports and has been proven on customer silicon operating faster than 10 Gb/s. One 10k-gate ULTRA module can test any number of SerDes lanes, and a TAP (or IEEE 1500 WTAP) can interface to any number of ULTRA modules.
Features and Benefits
- Jitter measurement with sub-picosecond accuracy: Histogram or RMS, HF jitter with golden PLL cut-off, duty cycle distortion, transition-density dependent delay.
- Waveshape measurement: Slew rate or 20 to 80% transition time and amplitude.
- Lane performance measurement: Bit errors in all lanes simultaneously, BER in multiple lanes simultaneously.
- Jitter tolerance parameters measurement: Mean sampling instant, systematic sampling errors in receiver, jitter in recovered clock.
- Design and test automation: RTL insertion and testbench generation, characterization and production tests, repeatability analysis
We have training courses available for Tessent products in our training centers around the world, online, or at your site. Tessent training courses