Tessent SerdesTest
Tessent® SerdesTest provides complete, parametric, embedded test for multi-Gb/s SerDes. It measures waveshape, many types of jitter, and various jitter tolerance parameters, all in less than 200 ms, including test set-up and on-chip comparison to test limits via an IEEE 1149.1 TAP interface.
Tessent SerdesTest uses unlimited time-resolution analysis (ULTRA) patented technology connected to only the SerDes parallel ports and has been proven on customer silicon operating faster than 10 Gb/s. One 10k-gate ULTRA module can test any number of SerDes lanes, and a TAP (or IEEE 1500 WTAP) can interface to any number of ULTRA modules.
Product Demo
Tessent SerdesTest
This presentation describes the features and capabilities of Mentor Graphics built-in self-tests for on-chip measurement of SerDes performance and just about any other IC timing. It performs the fastest tests, provides the most design and test automation, and allows unique diagnostic measurements.
Features and Benefits
- Jitter measurement with sub-picosecond accuracy: Histogram or RMS, HF jitter with golden PLL cut-off, duty cycle distortion, transition-density dependent delay.
- Waveshape measurement: Slew rate or 20 to 80% transition time and amplitude.
- Jitter tolerance parameters measurement: Mean sampling instant, systematic sampling errors in receiver, jitter in recovered clock.
- Lane performance measurement: Bit errors in all lanes simultaneously, BER in multiple lanes simultaneously.
- Design and test automation: RTL insertion and testbench generation, characterization and production tests, repeatability analysis
Related
Tessent SiliconInsight®
Tessent SerdesTest includes Tessent SiliconInsight Mixed-Signal solution. With this interactive capability, any of the supported SerDes embedded tests can be instantly run on a PC or tester. Tessent SiliconInsight
Datasheet
Toolbox
Contact Mentor Graphics
- Tessent SerdesTest Info Request or call toll free: 1-800-547-3000