The Tessent® SiliconInsight® solution provides an automated interactive environment for test bring-up, debug, and silicon characterization of devices containing Tessent BIST or Tessent IJTAG test structures..
Tessent SiliconInsight can greatly increase productivity for chip designers and test engineers during silicon validation and debug, speeding time-to-market. Tessent SiliconInsight reduces test and silicon bring-up time with interactive debug and characterization for benchtop environments. Tessent SiliconInsight enables Memory BIST datalogging.
Features and Benefits
- Increase productivity during critical silicon validation and debug phases.
- Benchtop environment enables low-cost, high-availability characterization.
- Interactive capabilities for controlling, debugging, and characterizing BIST-tested memories, logic, PLLs, and SerDes.
- Characterize the impact of test scheduling.
- Execute tests and collect data for any selection and order of BIST-tested blocks on the device.
- Characterize and debug devices with IEEE 1687 IJTAG instruments (requires Tessent IJTAG).
- Benchtop support through standard 1149.1 interface. Shmoo capability of power and clock through GPIB.
- Generate memory bitmaps from ATE fail data for devices with Enhanced Stop On Error (ESOE) Memory BIST.
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We have training courses available for Tessent products in our training centers around the world, online, or at your site. Tessent training courses