Tessent® SoCScan complements the Mentor Graphics ATPG solutions, Tessent TestKompress® and Tessent FastScan™, by providing an environment to insert a hierarchical scan and clock control infrastructure for at-speed testing and effective test reuse.
The hierarchical solution scales with design size, speed, and power, providing an integrated solution for the accurate and efficient at-speed testing of nanometer SoC designs. Test pattern generation times are reduced because individual cores in isolation need only be considered by Tessent FastScan or Tessent TestKompress. A hierarchical test flow is also crucial in managing low power designs.
Features and Benefits
- BurstMode test timing architecture provides effective at-speed test application and power control.
- Comprehensive RTL automation flow for fast test integration.
- Automatically integrates Tessent TestKompress EDT logic.
- Automatically creates procedure files and control scripts for Tessent TestKompress and Tessent FastScan pattern generation.
- IEEE 1500–compliant distributed test access architecture and patented core shared isolation for hierarchical test generation and application.
We have training courses available for Tessent products in our training centers around the world, online, or at your site. Tessent training courses