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Tessent TestKompress

Tessent® TestKompress® delivers the highest quality deterministic scan test with the lowest manufacturing test cost. The solution uses a patented on-chip compression technique to create scan pattern sets that have dramatically less test data volume and reduced test time on the automatic test equipment.

Highlights

  • Thorough testing of digital logic with scan-based patterns.
  • Fast pattern generation through high-performance ATPG algorithms and distributed processing.
  • A wide variety of fault models, including stuck-at, transition, path delay, multiple-detect, and more provide a thorough test program applicable to smaller geometry technologies.
  • Part of the Cell-Aware test methodology, which targets layout-derived, transistor level defects within cells
  • Supports low pin count test strategies (as few as one scan channel).
  • Failure files can be analyzed with Tessent Diagnosis and Tessent YieldInsight.

Award-Winning Technology

Product of the Year: Electronic Product2001. Product of the Year: Electronic Product

Best-in-Test: Test & Measurement  World2002. Best-in-Test: Test & Measurement World

Donald O. Pederson Award – IEEE2006. Donald O. Pederson Award – IEEE

Best-in-Test: Test & Measurement  World2008. Best-in-Test Honorable Mention: Test & Measurement World

Test-of-Time: Test & Measurement World2009. Test-of-Time: Test & Measurement World

Best-in-Test: Test & Measurement  World2013. Best in Test Winner: Tessent® TestKompress® with Cell-Aware ATPG

Best-of-West2013. Best of West Winner: Tessent® TestKompress® with Cell-Aware ATPG

ijtag2013. IJTAG Winner: IC Design Tools

ijtag2013. IJTAG Finalist: Golden Mousetrap Awards

elektra2013. Elektra Winner: Tessent TestKompress with Cell-Aware Technology

Related Products

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Tessent TestKompress can be used with Tessent SoCScan to take advantage of the Mentor Graphics automated hierarchical test integration and test generation flow. Tessent SoCScan makes use of shared isolation and capture-by-domain technologies to deliver independent core-level ATPG and chip-level pattern reuse.

Tessent IJTAG

Tessent ® IJTAG provides automation to support the emerging IEEE P1687 (IJTAG) standard for plug-and-play IP integration. Tessent TestKompress can make use of IJTAG to efficiently describe the tasks, which setup the design for subsequent tests, as well as tasks, which need to be run after completion of the test execution. Tessent IJTAG

Tessent LBIST

Tessent TestKompress can be used as a stand-alone test strategy or in conjunction with Tessent LBIST. The combination of the two solutions enables application of any combination of pseudorandom, deterministic, or compressed deterministic patterns. This provides the maximum flexibility for achieving the most effective test time versus quality optimization. Tessent LogicBIST

Tessent Training

We have training courses available for Tessent products in our training centers around the world, online, or at your site. Tessent training courses

Tessent TestKompress with Cell-Aware Testing
Mentor Graphics

"Cell-aware" automatic test pattern generation is being used to find the defects that occur within cells. Tessent TestKompress automates the analysis of cell libraries with a tool called CellModelGen and a language for creating user-defined fault models. This cell-aware methodology uses the physical characterization of cells to generate test patterns deterministically for potential defect locations. Learn more

 
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