Scan logic diagnosis is a powerful tool to help failure analysis engineers determine the root cause of a failing die. Yield engineers, on the other hand, are interested in statistical analysis of volumes of high-quality diagnosis results to determine yield limiters. To be of value for both engineers, a diagnosis tool needs to be:

• Accurate
• With high resolution, and...
• Meaningful defect classifications

Significant improvements have been made in scan logic diagnosis algorithms. However, the defect classifications, accuracy, and resolution provided by diagnosis tools are, in general, insufficient for effective yield and failure analysis. Through layout information Tessent™ Diagnosis improvements all three items, becoming a powerful tool in the hands of the failure analysis and yield engineer.

Layout information enables Tessent Diagnosis to improve accuracy and resolution by 70% to 85% depending on the defect type and allows layout-validated defect types. More meaningful reporting for example on the polygon level prepares the diagnosis results for direct use by engineers.

In the appendix, we discuss layout-aware flows and file formats, and summarize Tessent Diagnosis’ true layout-aware approach.