Designers of large System-On-Chip (SOC) chips have increasingly adopted hierarchical design practices in order to more efficiently complete work at the core level and simplify integration at the SOC level. Design-For-Test tasks such as test insertion, pattern generation and SOC integration benefit from the same hierarchical approach. The Tessent SoCScan toolset automates the work and flow required to insert test logic, isolate cores, integrate cores into the SOC and reuse core level patterns at the SOC level providing all the benefits of a hierarchical DFT flow.