This white paper provides a high level overview of the Mentor reference flow for ARM architecture.

Customers are integrating single or multiple ARM(r) Cortex(tm)-A15 processors into their SoC designs in order to take advantage of this industry-leading IP. In order to perform manufacturing test for the SoC, a test strategy needs to be adopted and the corresponding DFT implemented to achieve that test strategy. Traditionally, it has been up to the design-for-test (DFT) engineer to understand the test strategy and implement the DFT associated with it.

With the introduction of this jointly developed Mentor reference flow for ARM architecture, DFT engineers now have a guide so they can effectively and efficiently test designs that include the ARM Cortex-A15 processor.